VU Midterm Past Papers

CS501 — Advanced Computer Architecture — Midterm Past Papers & Solved MCQs

38 solved midterm past paper MCQs for CS501 (Advanced Computer Architecture) at Virtual University, each with the correct answer marked. Use them to learn the VU question style and test your recall. An independent study tool — not affiliated with VU.

Prefer a summary first? Read the CS501 midterm handout.

Q1. I multiplexer. is used to decide which value is transferred to be written back to the register file.
- A.ot
- B.of
- C.or
- D.oo✓ Correct
Q2. Select the correct option
- A.if (R2 == 0)
- B.if (R1>0)
- C.if (R1==0)✓ Correct
- D.if (R1<0)
Q3. case of SRC processor, bits of IR (instruction register) are reserved for the op-code.
- A.Y
- B.111015
- C.27 10 31✓ Correct
- D.59 to 63
Q4. i of the given RTL descriptions is used to represent "load register relative (Idr)" instruction?
- A.(0p<4..0>= 6): R [ra] — rel
- B.(0p<4..0>= 2): R [ra] «— M [rel]✓ Correct
- C.(0p<4..0>= 3) : M [disp] « R [ra]
- D.(op<4..0>= 4) : M[rel] «< RJ[ra]
Q5. i field of the machine language instruction is the "type of operation” that is to be performed?
- A.Op-code (or the operation code)✓ Correct
- B.CPU registers
- C.Memory cells
- D.1/0 locations
Q6. i of the following control signals is NOT activated during instruction fetch operation?
- A.PCout
- B.of✓ Correct
- C.h
- D.Cout
Q7. case of FALCON-A, instructions are present which are not present in the SRC processor.
- A.create and destroy
- B.in and out✓ Correct
- C.open and close
- D.read and write
Q8. - functionality is performed by the instruction “str R8, 34” of SRC?
- A.It will load the register R8 with the contents of the memory location M [PC+34]
- B.It will load the register R8 with the contents of the memory location M [34]
- C.It will store the register R8 contents to the memory location M [PC+34]
- D.It will store the register R8 contents to the memory location M [34]✓ Correct
Q9. I is the working of Processor Status Word (PSW)?
- A.To hold the current status of the processor✓ Correct
- B.To hold the address of the current process
- C.To hold the instruction that the computer is currently processing
- D.To hold the address of the next instruction in memory that is to be executed
Q10. - signal for RTL "IR <-- MBR" will be
- A.MBRout, LIR✓ Correct
- B.BN
- C.RB
- D.PCout, LIR
Q11. I does the instruction “Idr R3, 58" of SRC do?
- A.It will load register R3 with the contents of the memory location M[PC+58]✓ Correct
- B.It will load register R3 with the relative address itself (PC+58)
- C.It will store register R3 contents to the memory location M[PC+58]
- D.It will store the value of register R3 at the relative address itself (PC+58)
Q12. I status register of the 68000 has condition codes.
- A.of
- B.oo
- C.or✓ Correct
- D.ot
Q13. i of the instruction is used to load register from memory using a relative address?
- A.Id instruction
- B.Idr instruction✓ Correct
- C.lar instruction
- D.str instruction
Q14. i the type instructions, we require a register to hold the data that is to be loaded from the memory, or stored back to the memory
- A.of
- B.Control
- C.load/store✓ Correct
- D.Branch
Q15. CPU design, creates or forms the interface between the data path and the control unit.
- A.Busses
- B.ot
- C.Control Signal✓ Correct
- D.Cache
Q16. | control signal enables the input to the PC for receiving a value that is currently on the internal processor bus.
- A.oo✓ Correct
- B.ot
- C.of
- D.or
Q17. instruction format of EAGLE processor, there is no field reserved for operands.
- A.Type A
- B.Type B
- C.Type C
- D.Type Z✓ Correct
Q18. Type C instruction of SRC, bits are allocated for constant value.
- A.of
- B.oo✓ Correct
- C.ot
- D.or
Q19. he instruction will load the register R3 with the contents of the memory location M [PC+56
- A.lar R3, M[56]
- B.1dr R3, M[56]
- C.Idr R3, 56✓ Correct
- D.Ir R3, [56]
Q20. FALCON-A instruction format of TYPE-2 constants and variable should be in the range of
- A.132 to +131
- B.-164 to +163
- C.3210 +31
- D.128 to +127✓ Correct
Q21. a Falcon-A assembly program, labels are used to implement jump.
- A.Direct
- B.Indirect
- C.Relative✓ Correct
- D.Displacement
Q22. is a register which takes input from the ALSU as a memory address to be accessed and transfers the memory contents on that location onto the memory sub-system.
- A.PC
- B.MBR
- C.MAR✓ Correct
- D.IR
Q23. pipe-lined processors, there should be a port register file so that if the register write and register read stages overlap, they can be performed in parallel.
- A.of
- B.oo✓ Correct
- C.or
- D.oF
Q24. i of the following registers is used as an implicit operand in MUL/DIV instruction of Falcon-A?
- A.oo✓ Correct
- B.o°
- C.of
- D.ol
Q25. | instruction is used to divide a register value by the immediate value in FALCON-E processor.
- A.or
- B.o-
- C.Dil
- D.divim✓ Correct
Q26. i one of the following control signals causes the data from the bus to be read into the register MAR.
- A.MARout
- B.h
- C.Di
- D.None of the given✓ Correct
Q27. i one of the following operations is NOT performed by using miscellaneous instructions?
- A.Clearing all registers
- B.Stopping the processor
- C.oT✓ Correct
- D.Returning from a procedure
Q28. set the value of micro-PC from branch address, the value of 4 to 1 multiplexer is .
- A.of
- B.or
- C.ot
- D.Di✓ Correct
Q29. i of the following branch instructions has a condition which is always executed?
- A.of
- B.«0
- C.oo
- D.JMI✓ Correct
Q30. i type of instructions enables mathematical computations?
- A.Arithmetic✓ Correct
- B.Control
- C.Data transfer
- D.Numeric
Q31. LIW stands for
- A.Variable Length Instruction Word
- B.Very Long Instruction Word✓ Correct
- C.Very Long Instruction Width
- D.Variable Length Instruction Width
Q32. i of the following is NOT related to the architecture of a computer?
- A.Instruction set
- B.Control signals✓ Correct
- C.I/O mechanisms
- D.Memory addressing modes
Q33. SRC, which of the following is a notation which is used to represent 32-bit memory word stored at address starting from 56?
- A.M[56]<31..0> := M[56] M[57] M[58] M[59]✓ Correct
- B.M[56]<0..31> := M[56] M[57] M[58] M[59]
- C.M[56]<0..31> := M[59] M[58] M[57] M[56]
- D.M[56]<31..0> := M[59] M[58] M[57] M[56]
Q34. i of the following RTL descriptions is used for specifying the operation of an SRC instruction?
- A.IR<31..27>✓ Correct
- B.IR<22..26>
- C.IR<21..17>
- D.IR<21..0>
Q35. i the two approaches available to design a control unit, hardwired approach is relativel as compared to micro-programming.
- A.)
- B.-
- C.Faster✓ Correct
- D.Better
Q36. I MAR is connected directly to the .
- A.oo"
- B.CPU internal bus✓ Correct
- C.CPU external bus
- D.LIC
Q37. In a processor, is responsible for the synchronization of internal as well as external events.
- A.Memory Unit
- B.Data Unit
- C.Arithmetic & Logical Unit
- D.Control Unit✓ Correct
Q38. i of the following is not a part of processor state?
- A.ot
- B.of
- C.oT
- D.Registers✓ Correct

VU Midterm Past Papers

CS501 — Advanced Computer Architecture — Midterm Past Papers & Solved MCQs

Prefer a summary first? Read the CS501 midterm handout.

Q1. I multiplexer. is used to decide which value is transferred to be written back to the register file.
- A.ot
- B.of
- C.or
- D.oo✓ Correct
Q2. Select the correct option
- A.if (R2 == 0)
- B.if (R1>0)
- C.if (R1==0)✓ Correct
- D.if (R1<0)
Q3. case of SRC processor, bits of IR (instruction register) are reserved for the op-code.
- A.Y
- B.111015
- C.27 10 31✓ Correct
- D.59 to 63
Q4. i of the given RTL descriptions is used to represent "load register relative (Idr)" instruction?
- A.(0p<4..0>= 6): R [ra] — rel
- B.(0p<4..0>= 2): R [ra] «— M [rel]✓ Correct
- C.(0p<4..0>= 3) : M [disp] « R [ra]
- D.(op<4..0>= 4) : M[rel] «< RJ[ra]
Q5. i field of the machine language instruction is the "type of operation” that is to be performed?
- A.Op-code (or the operation code)✓ Correct
- B.CPU registers
- C.Memory cells
- D.1/0 locations
Q6. i of the following control signals is NOT activated during instruction fetch operation?
- A.PCout
- B.of✓ Correct
- C.h
- D.Cout
Q7. case of FALCON-A, instructions are present which are not present in the SRC processor.
- A.create and destroy
- B.in and out✓ Correct
- C.open and close
- D.read and write
Q8. - functionality is performed by the instruction “str R8, 34” of SRC?
- A.It will load the register R8 with the contents of the memory location M [PC+34]
- B.It will load the register R8 with the contents of the memory location M [34]
- C.It will store the register R8 contents to the memory location M [PC+34]
- D.It will store the register R8 contents to the memory location M [34]✓ Correct
Q9. I is the working of Processor Status Word (PSW)?
- A.To hold the current status of the processor✓ Correct
- B.To hold the address of the current process
- C.To hold the instruction that the computer is currently processing
- D.To hold the address of the next instruction in memory that is to be executed
Q10. - signal for RTL "IR <-- MBR" will be
- A.MBRout, LIR✓ Correct
- B.BN
- C.RB
- D.PCout, LIR
Q11. I does the instruction “Idr R3, 58" of SRC do?
- A.It will load register R3 with the contents of the memory location M[PC+58]✓ Correct
- B.It will load register R3 with the relative address itself (PC+58)
- C.It will store register R3 contents to the memory location M[PC+58]
- D.It will store the value of register R3 at the relative address itself (PC+58)
Q12. I status register of the 68000 has condition codes.
- A.of
- B.oo
- C.or✓ Correct
- D.ot
Q13. i of the instruction is used to load register from memory using a relative address?
- A.Id instruction
- B.Idr instruction✓ Correct
- C.lar instruction
- D.str instruction
Q14. i the type instructions, we require a register to hold the data that is to be loaded from the memory, or stored back to the memory
- A.of
- B.Control
- C.load/store✓ Correct
- D.Branch
Q15. CPU design, creates or forms the interface between the data path and the control unit.
- A.Busses
- B.ot
- C.Control Signal✓ Correct
- D.Cache
Q16. | control signal enables the input to the PC for receiving a value that is currently on the internal processor bus.
- A.oo✓ Correct
- B.ot
- C.of
- D.or
Q17. instruction format of EAGLE processor, there is no field reserved for operands.
- A.Type A
- B.Type B
- C.Type C
- D.Type Z✓ Correct
Q18. Type C instruction of SRC, bits are allocated for constant value.
- A.of
- B.oo✓ Correct
- C.ot
- D.or
Q19. he instruction will load the register R3 with the contents of the memory location M [PC+56
- A.lar R3, M[56]
- B.1dr R3, M[56]
- C.Idr R3, 56✓ Correct
- D.Ir R3, [56]
Q20. FALCON-A instruction format of TYPE-2 constants and variable should be in the range of
- A.132 to +131
- B.-164 to +163
- C.3210 +31
- D.128 to +127✓ Correct
Q21. a Falcon-A assembly program, labels are used to implement jump.
- A.Direct
- B.Indirect
- C.Relative✓ Correct
- D.Displacement
Q22. is a register which takes input from the ALSU as a memory address to be accessed and transfers the memory contents on that location onto the memory sub-system.
- A.PC
- B.MBR
- C.MAR✓ Correct
- D.IR
Q23. pipe-lined processors, there should be a port register file so that if the register write and register read stages overlap, they can be performed in parallel.
- A.of
- B.oo✓ Correct
- C.or
- D.oF
Q24. i of the following registers is used as an implicit operand in MUL/DIV instruction of Falcon-A?
- A.oo✓ Correct
- B.o°
- C.of
- D.ol
Q25. | instruction is used to divide a register value by the immediate value in FALCON-E processor.
- A.or
- B.o-
- C.Dil
- D.divim✓ Correct
Q26. i one of the following control signals causes the data from the bus to be read into the register MAR.
- A.MARout
- B.h
- C.Di
- D.None of the given✓ Correct
Q27. i one of the following operations is NOT performed by using miscellaneous instructions?
- A.Clearing all registers
- B.Stopping the processor
- C.oT✓ Correct
- D.Returning from a procedure
Q28. set the value of micro-PC from branch address, the value of 4 to 1 multiplexer is .
- A.of
- B.or
- C.ot
- D.Di✓ Correct
Q29. i of the following branch instructions has a condition which is always executed?
- A.of
- B.«0
- C.oo
- D.JMI✓ Correct
Q30. i type of instructions enables mathematical computations?
- A.Arithmetic✓ Correct
- B.Control
- C.Data transfer
- D.Numeric
Q31. LIW stands for
- A.Variable Length Instruction Word
- B.Very Long Instruction Word✓ Correct
- C.Very Long Instruction Width
- D.Variable Length Instruction Width
Q32. i of the following is NOT related to the architecture of a computer?
- A.Instruction set
- B.Control signals✓ Correct
- C.I/O mechanisms
- D.Memory addressing modes
Q33. SRC, which of the following is a notation which is used to represent 32-bit memory word stored at address starting from 56?
- A.M[56]<31..0> := M[56] M[57] M[58] M[59]✓ Correct
- B.M[56]<0..31> := M[56] M[57] M[58] M[59]
- C.M[56]<0..31> := M[59] M[58] M[57] M[56]
- D.M[56]<31..0> := M[59] M[58] M[57] M[56]
Q34. i of the following RTL descriptions is used for specifying the operation of an SRC instruction?
- A.IR<31..27>✓ Correct
- B.IR<22..26>
- C.IR<21..17>
- D.IR<21..0>
Q35. i the two approaches available to design a control unit, hardwired approach is relativel as compared to micro-programming.
- A.)
- B.-
- C.Faster✓ Correct
- D.Better
Q36. I MAR is connected directly to the .
- A.oo"
- B.CPU internal bus✓ Correct
- C.CPU external bus
- D.LIC
Q37. In a processor, is responsible for the synchronization of internal as well as external events.
- A.Memory Unit
- B.Data Unit
- C.Arithmetic & Logical Unit
- D.Control Unit✓ Correct
Q38. i of the following is not a part of processor state?
- A.ot
- B.of
- C.oT
- D.Registers✓ Correct