CS501 — Midterm Summary (Lectures 1–22)

📘 Lecture 1 — Introduction

📖 Overview: This lecture introduces the fundamental concepts of computer architecture, distinguishing it from computer organization and design. It establishes the definition of a general-purpose digital computer, explains the stored program concept and the fetch-execute cycle, and explores the different levels of abstraction in digital design. This foundational knowledge is essential for understanding how computers are designed and how they operate at various levels of detail.

🗂️ Topics Covered

This lecture covers the distinction between computer architecture, organization, and design; levels of abstraction in digital design from the PMS level down to the mask level; the definition and essential elements of a general-purpose digital computer; the stored program concept and the fetch-execute process; the concept of an Instruction Set Architecture (ISA); perspectives of different people about computers including users, programmers, computer architects, and logic designers; and tools and views relevant to each perspective.

📝 Lecture Summary

Introduction

This course is about Computer Architecture. The lecture begins by explaining key terms, starting with the definition of a computer for the purposes of this course.

The General Purpose Digital Computer

A computer is defined as "An electronic device, operating under the control of instructions stored in its own memory unit, that can accept data (input), process data arithmetically and logically, produce output from the processing, and store the results for future use." For this course, the term computer refers to a general-purpose digital computer that can perform a variety of arithmetic and logic tasks, as opposed to dedicated computers like those in automobiles.

The Computer as a System

A system is a collection of elements or components working together on one or more inputs to produce one or more desired outputs. Systems include chemical, optical, biological, electrical, and mechanical systems. Digital systems are a subset of electrical systems where inputs and outputs are digital quantities. General-purpose digital computers are a subset of digital systems, and this course focuses on them.

Essential Elements of a General Purpose Digital Computer

A modern general-purpose digital computer has three main components: a memory subsystem, an input/output subsystem, and a central processing unit (CPU) . Programs are stored in memory, instruction execution occurs in the CPU, and communication with the external world is achieved through the I/O subsystem.

Architecture

The word architecture means "the art or science of building" or "a method or style of building."

Computer Architecture

This term was first used in 1964 by Amdahl, Blaauw, and Brooks at IBM. They defined it as "The structure of a computer that a machine language programmer must understand to write a correct (time independent) program for that machine." By architecture, they meant the programmer-visible portion of the instruction set. The study of computer architecture includes:

• A study of the structure of a computer
• A study of the instruction set of a computer
• A study of the process of designing a computer

Computer Organization versus Computer Architecture

Architecture refers to the attributes of a computer that are visible to a programmer, including the instruction set, the number of bits used to represent various data types, I/O mechanisms, and memory addressing modes. Organization refers to the operational units of a computer and their interconnections that realize the architectural specifications, including control signals, interfaces between the computer and its peripherals, and the memory technology used. It is an architectural issue whether a computer will have a specific instruction, while it is an organizational issue how that instruction will be implemented.

Computer Architect

A computer architect is a person who designs computers.

Design

Design is defined as "The process of devising a system, component, or process to meet desired needs." In standard engineering usage, design is a process—a decision-making process (often iterative) in which basic sciences, mathematical concepts, and engineering sciences are applied to convert a given set of resources optimally to meet a stated objective.

Knowledge base of a computer architect

Computer design experts are familiar with the structure of a computer, the instruction set of a computer, and the process of designing a computer. It is not the job of a single person to design a computer from scratch; there are a number of levels of computer design, with domain experts carrying out the design activity for each level.

Digital Design: Levels of Abstraction

The design of a digital computer is viewed at several levels of abstraction:

Processor-Memory-Switch level (PMS level) This is the highest level, where an architect views the system. It is a description of the system components and their interconnections, specified in the form of a block diagram.

Instruction Set Level This level defines the function of each instruction, emphasizing the behavior of the system rather than the hardware structure.

Register Transfer Level Next to the ISA level, the hardware structure becomes visible. Basic elements at this level include registers, multiplexers, decoders, buses, and buffers. The above three levels relate to "system design."

Logic Design Level Also called the gate level, the basic elements are gates and flip-flops. Hardware structure predominates over behavior. This level relates to "logic design."

Circuit Level Key elements at this level are resistors, transistors, capacitors, and diodes.

Mask Level The lowest level, dealing with silicon structures and their layout that implement the system as an integrated circuit. The above two levels relate to "circuit design."

The focus of this course will be the register transfer level and the instruction set level, though it will also deal with the PMS level and the Logic Design Level.

Objectives of the course

This course will provide students with an understanding of the various levels of studying computer architecture, with emphasis on the instruction set level and register transfer level. Students will be able to use basic combinational and sequential building blocks to design larger structures like ALUs, memory subsystems, and I/O subsystems. It will help them understand the various approaches used to design CPUs of the RISC and CISC types, as well as the principles of cache memories.

Important topics to be covered

Topics include a review of computer organization, classification of computers and their instructions, machine characteristics and performance, design of a Simple RISC Computer (SRC), advanced topics in processor design, I/O subsystems, ALU implementation, and memory subsystems.

A brief review of Computer Organization Perceptions of Different People about Computers

There are various perspectives on a computer depending on the person viewing it. Generally, four views are considered for understanding the machine.

The User’s View A user employs the computer to perform useful work through application software. At this level, one is only concerned with things like speed, storage capacity, and peripheral device behavior. The internal structure is made obscure by the operating system interface.

The Programmer’s View By "programmer," we imply machine or assembly language programmers responsible for implementing software.

Machine Language consists of all the primitive instructions a computer understands and can execute, expressed as strings of 1s and 0s. It is the computer’s native language and the lowest level language.

Instruction Set is a collection of all possible machine language commands a computer can understand and execute. Every processor has its own unique instruction set.

Assembly Language is a substitute symbolic representation using "English-like" key words called mnemonics. A pure assembly language has a one-to-one correspondence between machine instructions and statements in the assembly language, though there are exceptions.

🔑 Definition — Mnemonics: English-like keywords used in assembly language to represent machine instructions.

Users of Assembly Language include:

• The machine designer, who needs to understand trade-offs in instruction set design.
• The compiler writer, who must be familiar with the machine language to produce correct and optimized code.
• The writer of time or space critical code, as compilers may not always produce optimal code.
• Special purpose or embedded processor programmers, for whom higher-level languages may not be appropriate.

Useful tools for assembly language programmers include:

• The assembler: translates assembly language to machine language. A cross assembler runs on one processor and translates code for another processor.
• The linker: combines separate modules of functionality into a single module for loading and execution, enabling modularity.
• The debugger or monitor: a program used to aid in detecting runtime, syntax, or logical errors. It provides functionality like displaying/altering memory and registers, disassembly, single stepping, and breakpoints.
• The development system: a complete set of hardware and software tools including assemblers, linkers, loaders, debuggers, compilers, emulators, hardware-level debuggers, and logic analyzers.

Difference between Higher-Level Languages and Assembly Language: High-level languages are generally used to develop application software. There is a many-to-many mapping between HLL and assembly language constructs. HLLs provide primitive data types and type checking. At the machine level, there is generally no type checking; the machine only sees strings of bits, and instructions interpret these strings as types.

The Stored Program Concept This fundamental concept states that the program is stored with data in the computer’s memory, and the computer can manipulate it as data. The sequence of instructions to perform some useful task is called a program.

General Operation of a Stored Program Computer Machine language programs are brought into memory and executed instruction by instruction. The instruction to be executed is fetched from memory and temporarily stored in a CPU register called the instruction register (IR) . The program counter (PC) , also called the instruction pointer, holds the address of the next instruction to be executed.

When execution of an instruction is completed, the contents of the PC are placed on the address bus. The memory places the instruction on the data bus. The CPU puts this instruction into the IR to decode and execute. While this instruction is decoded, its length is determined and the PC is incremented by that length. In RISC machines, instruction length is fixed, so the PC is always incremented by a fixed number. For branch instructions, the PC contents are replaced by the address in the branch instruction. The current processor status is stored in a register called the Processor Status Word (PSW), also called the flag register. This entire process of reading memory, incrementing the PC, and decoding the instruction is known as the Fetch and Execute principle.

The Concept of Instruction Set Architecture (ISA) The programmer’s view is limited to the set of all assembly instructions a computer can understand, along with the resources these instructions help manage (memory space and programmer-accessible registers). This set of instructions and resources together form the instruction set architecture (ISA) . The ISA serves as an interface between the program and the functional units of a computer.

The Computer Architect’s View The computer architect’s view is concerned with designing the entire system and ensuring its optimum performance. The computer architect:

• Designs the ISA for optimum programming utility and performance
• Designs hardware for best implementation of instructions
• Uses performance measurement tools like benchmark programs
• Balances performance of building blocks (CPU, memory, I/O, interconnections)
• Strives to meet performance goals at the lowest possible cost

Useful tools include software models, simulators, emulators, performance benchmark programs, specialized measurement programs, data flow and bottleneck analysis, subsystem balance analysis, and cost analysis.

The Logic Designer’s View The logic designer is responsible for designing the machine at the logic gate level. This design process determines whether the computer architect meets cost and performance goals. The computer architect and logic designer must work collaboratively.

Useful Tools for the Logic Designer include CAD tools (logic design and simulation packages, PCB layout tools, IC design and layout tools), logic analyzers, oscilloscopes, and hardware development systems.

The Concept of the Implementation Domain The collection of hardware devices with which the logic designer works is termed the implementation domain. Logic gate implementation domains may include VLSI on silicon, TTL or ECL chips, Gallium arsenide chips, PLAs, or fluidic logic/optical switches. Interconnection domains may include poly-silicon lines in ICs, conductive traces on a PCB, electrical cable, or optical fiber.

Classical logic design versus computer logic design Traditional finite state machine design techniques are not suitable for designing a computer, even though a computer is a finite state machine, because the computer can assume hundreds of states.

Sequential Logic Circuit Design Traditional sequential circuit design involves creating a state diagram, eliminating redundant states, translating into a next state table, making state assignments, creating a transition table, completing excitation tables, determining excitation equations through minimization, and drawing the logic circuit.

Computer Logic Design Because there is a natural separation between the data path (storage cells, arithmetic/logic components, and interconnections) and the control path (circuitry managing data path information flow) in a digital computer, a modular approach can be used. Well-defined logic blocks such as multiplexers, decoders, and adders can be used repeatedly.

Two Views of the CPU Program Counter Register To a programmer, the program counter is just a register (e.g., 32 bits). To a logic designer, the program counter is implemented as an array of D flip-flops, with control signals like PCout (gating contents onto the address bus) and PCin (storing contents from the bus on the leading edge of the clock signal).

⭐ Key Takeaways

The most critical concepts from this lecture are the clear distinction between computer architecture (programmer-visible attributes like instruction set) and computer organization (how those attributes are implemented with hardware). The stored program concept and the Fetch-Execute cycle (fetch instruction from memory, increment PC, decode, and execute) form the foundation of all general-purpose digital computers. The multiple levels of abstraction—from PMS level to mask level—allow different experts to design different aspects of a computer. The ISA serves as the critical interface between software and hardware, defining what a programmer can access and control. Finally, understanding the different perspectives (user, programmer, computer architect, logic designer) is essential for grasping the full scope of computer system design.

🧠 Quick Revision Questions

1. What is the difference between computer architecture and computer organization? Give two examples of each.
2. Describe the Fetch-Execute cycle, including the roles of the Program Counter (PC), Instruction Register (IR), and Processor Status Word (PSW).
3. What are the six levels of abstraction in digital design, and which levels are the primary focus of this course?
4. What is the Stored Program Concept, and why is it fundamental to general-purpose digital computers?
5. What is an Instruction Set Architecture (ISA), and what does it include from a programmer's perspective?

📘 Lecture 2 — Instruction Set Architecture

📖 Overview: This lecture explores the fundamental aspects of computer architecture by classifying instruction set architectures based on CPU operand storage mechanisms. It provides a comprehensive analysis of instruction formats, addressing modes, and the contrasting philosophies of RISC and CISC architectures, essential for understanding how processors execute programs.

🗂️ Topics Covered

The lecture begins with a taxonomy of computers and their instructions, covering accumulator, stack, and general-purpose register machines. It then examines instruction set features including essential elements of instructions, classifications by address count (4-address to 0-address), and comparisons based on code size and memory accesses. Addressing modes are thoroughly explained, followed by a detailed comparison of RISC and CISC architectures with their respective advantages and disadvantages.

📝 Lecture Summary

CLASSES OF INSTRUCTION SET ARCHITECTURE:

Processors can be classified based on how the CPU stores instructions and data. There are three primary types: Accumulator based machines, Stack based machines, and General purpose register (GPR) machines.

ACCUMULATOR BASED MACHINES use special registers called accumulators to hold one source operand and the result of arithmetic or logic operations. Since the accumulator holds one operand, another register may hold the address of the second operand. Accumulator machines are also called 1-address machines. They employ a very small number of accumulator registers, generally only one. These were useful when memory was expensive, but their use is now severely limited for complex expressions.

🔑 Definition — Accumulator: A special register that collects (accumulates) data, holding one source operand and the result of an operation. 📐 Concept: Accumulator machines are 1-address machines because only the memory operand address needs to be specified; the accumulator is implicit. 💡 Why this matters: Understanding accumulator-based design explains why early computers had limited computation capabilities and why modern processors use multiple registers.

STACK BASED MACHINES organize registers as a last-in-first-out (LIFO) structure. Operands stored first (via push) can only be accessed last (via pop). Arithmetic operations pick operands from the top-of-the-stack (TOS) and push results back. Since operand addresses need not be specified, these are called 0-address machines.

🔑 Definition — Stack: A group of registers organized as a LIFO structure where operands are accessed in reverse order of storage. 📌 Example: In a self-service cafeteria, plates are stacked; the last plate placed on top is the first one taken (pop).

GENERAL-PURPOSE-REGISTER MACHINES have multiple registers within the CPU without dedicated functions. A small number of bits identify registers (e.g., 6 bits for 64 registers). CPU registers are faster than cache memory and more effectively used by compilers. Registers can hold variables, addresses, and pointers, reducing memory traffic.

🔑 Definition — General Purpose Registers: CPU registers without dedicated functions that can be used for data, addresses, or pointers. 💡 Why this matters: Modern processors use general-purpose registers because they significantly increase execution speed and reduce code size compared to memory-based operations.

INSTRUCTION SET

An instruction set is a collection of all possible machine language commands that a processor can understand and execute.

ESSENTIAL ELEMENTS OF COMPUTER INSTRUCTIONS:

There are four essential elements: the type of operation, the place to find source operands, the place to store results, and the source of the next instruction.

🔑 Definition — Op-code (Operation Code): The bit-pattern field in a machine language instruction that encodes the type of operation to be performed. 📌 Example: add cx, dx — the op-code for add is 0000; contents of dx are added to cx, result stored in cx.

Source operands can be located in CPU registers, memory cells, I/O locations, or be part of the instruction itself (immediate operands). The result can be stored in CPU registers, memory cells, or I/O locations. The next instruction is implicitly the next-in-sequence unless a branch occurs (conditional/unconditional, subroutine call, or interrupt service routine).

CLASSIFICATIONS OF INSTRUCTIONS:

Instructions are classified based on the number of addresses specified: 4-address, 3-address, 2-address, 1-address, and 0-address instructions.

4-address instructions specify addresses of two source operands, one destination operand, and the next instruction address. They are not common because the next instruction is usually sequential; used in micro-coded control units.

3-address instructions specify addresses of two source operands and one destination operand.

2-address instructions have three fields: op-code, one field for both source and destination operand, and another field for the second source operand. One field serves two purposes.

1-address instructions use an implicit accumulator register, requiring only one field for a source/destination operand address.

0-address instructions use a stack implicitly; only the op-code field is needed.

COMPARISON OF INSTRUCTION FORMATS:

Basis for comparison includes code size (affects storage requirements) and number of memory accesses (affects execution time).

Assumptions: 1 byte for op-code (256 instructions), 16 Mbyte memory address space, byte-addressable memory, 24-bit operand size, 24-bit address bus, 8-bit data bus.

HALF ADDRESSES

Half addresses refer to CPU register addresses, which require fewer bits than memory addresses. An instruction specifying one memory address and one CPU register is called a 1½-address instruction.

📌 Example: mov al, [34h]

THE PRACTICAL SITUATION

Real machines mix 3, 2, 1, 0, and 1½-address instructions. For example, the VAX 11 includes instructions from all classes.

CLASSIFICATION OF MACHINES ON THE BASIS OF OPERAND AND RESULT LOCATION:

Machines are classified based on whether ALU instructions use data from memory. Load-store machines (also called register-to-register machines) use only CPU registers for operands and results. Other machines may have register-memory or memory-memory instructions.

Load-Store Machines: Only load and store instructions access memory. Load fetches data into CPU registers; other instructions use these registers; store writes results back. Most RISC computers use this type.

Advantages: Instructions are simple and fixed in length, code generation is simple, all instructions take similar clock cycles.

Disadvantages: Higher instruction count (separate load/store instructions needed), fixed instruction size wastes bits for instructions not needing all fields.

Register-Memory Machines: Some operands in memory, some in registers. Typically use 1 or 1½ address format.

Advantages: No need to load memory operands first; easier encoding; better instruction bit usage.

Disadvantages: Operands not equivalent (one may have two functions); different size encoding may restrict register count; variable clock cycles per instruction.

Memory-Memory Machines: All three operands (2 source, 1 destination) in memory. Use 2-address or 3-address formats.

Advantages: Most compact instruction encoding; no CPU registers wasted.

Disadvantages: Variable instruction size makes decoding complex; varying cycles per instruction; slow memory accesses degrade performance.

📌 Example 1: Evaluate a = (b+c)*d – e with different address machines.

📌 Example 2: Evaluate z = 4(a+b) – 16(c+58) with different address machines.

FUNCTIONAL CLASSIFICATION OF INSTRUCTION SETS:

Instructions are classified into four categories: Data processing (ALU operations), Data storage (main memory access), Data movement (I/O), and Program flow control (branches, conditional/unconditional).

ADDRESSING MODES:

Addressing modes are the different ways the CPU generates the address of operands. The effective address is the binary bit pattern issued by the CPU to the memory.

Immediate Addressing Mode: Data is part of the instruction; no address calculation needed. Used only for source operands. Range for n-bit field: -2^(n-1) to +(2^(n-1)-1).

📌 Example: lda 123 — immediate operand 123 loaded into accumulator.

Direct Addressing Mode: The address of the operand is specified as a constant in the instruction. Address space limited by operand field size (2^operand field size locations).

📌 Example: lda [123] — operand fetched from memory address 123.

Indirect Addressing Mode: The instruction contains the address of a memory location that holds the address of the operand. Two memory accesses required. Useful for implementing pointers.

📌 Example: lda [[123]] — first access gets address from memory at 123, second access gets operand.

Register (Direct) Addressing Mode: Operand is in a CPU register; register address encoded in instruction. No memory access needed. Limited by number of CPU registers.

📌 Example: lda R2 — operand fetched from register R2.

Register Indirect Addressing Mode: A CPU register contains the address of the memory location holding the operand. Large address space (2^register size locations). Fewer memory accesses than indirect.

📌 Example: lda [R1] — register R1 holds memory address of operand.

Displacement Addressing Mode (also called based or indexed addressing): Effective address = constant (part of instruction) + value in CPU register. Useful for accessing arrays. Called indexed when constant is base and register holds index; based when constant is offset and register holds base address.

📌 Example: lda [R1 + 8] — R1 holds base address, 8 is added, operand fetched from effective address.

Relative Addressing Mode: Similar to indexed, but Program Counter (PC) holds the base address. Useful for 'short' jumps.

📌 Example: jump 4 — constant 4 added to PC to form target address.

RISC AND CISC ARCHITECTURES:

RISC (Reduced Instruction Set Computers) is a design philosophy focusing on reducing the number and complexity of instructions, though modern RISC machines may have complex instructions.

Common features of RISC machines:

• One instruction per clock period — achievable through pipelining
• Fixed size instructions — typically 32 bits
• CPU accesses memory only for Load and Store operations — all operands in CPU registers
• Simple and few addressing modes — reduces complex decoding
• Less work per instruction — allows reduced clock period T
• Improved usage of delay slots — executing next instruction while waiting for load/store/branch
• Efficient usage of Pre-fetching and Speculative Execution Techniques

🔑 Definition — Delay slot: The waiting time for a load/store to access memory or a branch to access the target instruction. 🔑 Definition — Speculative execution: Issuing instructions before knowing whether a branch will be taken, discarding results if speculation is wrong.

CISC (Complex Instruction Set Computers) has no underlying philosophy; it resulted from efforts to efficiently utilize memory and minimize execution time by adding more instruction formats and addressing modes.

Common attributes of CISC machines:

• More work per instruction — compact programs with more functionality
• Wide variety of addressing modes — e.g., 14 in MC68000, 25 in MC68020
• Variable instruction lengths and execution times per instruction
• Attempt to reduce the "semantic gap" — the gap between machine-level instructions and high-level language constructs

Disadvantages of CISC:

• Clock period T cannot be reduced beyond a certain limit due to complex circuits
• Complex addressing modes delay operand fetch from memory
• Difficult to make efficient use of speedup techniques like pipelining, pre-fetching, superscalar operation, and speculative execution

⭐ Key Takeaways

The most critical concepts from this lecture are: (1) Instruction set architectures are fundamentally classified by how the CPU stores operands—accumulator, stack, or general-purpose registers, each with distinct address formats (1-address, 0-address, and multiple-address). (2) The number of addresses in an instruction directly impacts code size and memory accesses, with 0-address instructions being most compact but requiring more memory accesses, while 1-address instructions balance efficiency. (3) Addressing modes determine how effective addresses are computed, with immediate, direct, indirect, register, indexed, and relative modes each offering different trade-offs between flexibility, address space, and memory access overhead. (4) RISC and CISC represent opposing design philosophies—RISC emphasizes simplicity, fixed instruction size, and register-to-register operations to enable pipelining and speculative execution, while CISC prioritizes instruction density and complex addressing to reduce the semantic gap between machine code and high-level languages. (5) The practical reality is that most modern processors incorporate features from multiple classifications, making it essential to understand the underlying trade-offs for performance analysis and compiler optimization.

🧠 Quick Revision Questions

1. What are the three main classes of instruction set architecture based on how the CPU stores instructions and data, and what address format does each use?

2. Compare the code size and number of memory accesses for 4-address, 2-address, 1-address, and 0-address instructions under the given assumptions (1-byte op-code, 3-byte addresses).

3. List and explain five commonly used addressing modes, providing an example for each and stating how many memory accesses are required.

4. What are the key differences between RISC and CISC architectures regarding instruction size, addressing modes, memory access patterns, and clock cycle characteristics?

5. Explain the concept of "delay slots" in RISC architecture and how "speculative execution" improves processor performance.

📘 Lecture 3 — Introduction to SRC Processor

📖 Overview: This lecture introduces performance measurement techniques for computer systems and presents the SRC (Simple RISC Computer) as an example processor to understand architectural concepts. It covers benchmark programs, performance metrics like MIPS and MFLOPS, and details the SRC’s notation, features, and instruction formats.

🗂️ Topics Covered

The lecture begins by discussing measures of performance including execution time, MIPS, MFLOPS, Whetstones, Dhrystones, and SPEC benchmarks. It then introduces the SRC processor with its register set, memory organization, and notation. The lecture concludes with a detailed examination of the four SRC instruction formats: Type A (no operation and stop), Type B (relative addressing load/store), Type C (direct/indexed load/store and ALU instructions), and shift instructions.

📝 Lecture Summary

Measures of performance: Performance testing

To test or compare machine performance, programs are run and their execution times measured. However, execution speed depends on the particular program. Standard programs called “benchmark programs” approximate real workloads. Actual execution time is measured by running these programs on the machines.

Commonly used measures of performance

The basic measure of performance is time. Common measures include Execution time, MIPS, MFLOPS, Whetstones, Dhrystones, and SPEC.

Execution time

Execution time is the time a processor takes to execute a given program. It depends on factors like I/O waits, instruction fetch times, and pipeline delays.

📐 Formula: Execution Time = IC × CPI × T Where:

• IC = instruction count
• CPI = average number of system clock periods to execute an instruction
• T = clock period

💡 Why this matters: This formula helps quantify processor performance, but using average CPI is a simplification.

MIPS (Millions of Instructions per Second)

MIPS measures millions of instructions executed per second.

📐 Formula: MIPS = IC / (ET × 10⁶)

💡 Why this matters: MIPS is not accurate for comparing different processors because architectural differences mean some machines require more instructions to perform the same job. For example, RISC machines have simpler instructions, so the same job requires more instructions.

MFLOPS (Millions of Floating Point Instructions per Second)

For computation-intensive applications, MFLOPS measures floating-point instruction execution. It has two advantages over MIPS:

• Floating point operations are complex, providing a better picture of hardware capabilities.
• Overheads (operand fetch, result storage) are effectively lumped with the floating point operations they support.

Whetstones

Whetstone was the first benchmark program, developed using statistics from the Whetstone Algol compiler. It tests floating point instructions. Performance is stated in MWIPS (millions of Whetstone instructions per second).

Dhrystones

Developed in 1984, Dhrystone is a small benchmark (about 100 high-level-language statements) that measures integer instruction performance, contrasting with Whetstone’s floating point focus.

Disadvantages of using Whetstones and Dhrystones

Both are now considered obsolete because:

• Small, fit in cache
• Obsolete instruction mix
• Prone to compiler tricks
• Difficult to reproduce results
• Uncontrolled source code

💡 Why this matters: Being small programs, they encourage ‘over-optimization’, and optimizing compilers can distort results.

SPEC

SPEC (System Performance Evaluation Cooperative) is an association defining standard benchmarks for fair processor evaluation. The suite includes:

• A compiler
• A Boolean minimization program
• A spreadsheet program
• Other programs stressing arithmetic processing speed
• Latest version: SPEC CPU2000

Advantages:

• Ease of publication
• Each benchmark carries the same weight
• SPEC ratio is dimensionless
• Not unduly influenced by long running programs
• Relatively immune to performance variation on individual benchmarks
• Provides a consistent and fair metric

An example computer: the SRC: “simple RISC computer”

The SRC (Simple RISC Computer) is introduced to facilitate understanding of design steps and concepts. It is simple yet complex enough to illustrate fundamentals.

SRC Introduction

Attributes of the SRC:

• 32 General Purpose Registers: R0, R1, ..., R31; each is 32 bits
• Two special purpose registers: Program Counter (PC) and Instruction Register (IR)
• Memory word size: 32 bits
• Memory space size: 2³² bytes
• Memory organization: 2³² × 8 bits (byte aligned)
• Memory accessed in 32-bit words (4 byte chunks)
• Big-endian byte storage used

Programmer’s View of the SRC: The figure shows 32, 32-bit CPU registers, two additional CPU registers (PC & IR), and main memory as 2³² 1-byte cells.

SRC Notation

Notation examples:

• R[3] means contents of register 3
• M[8] means contents of memory location 8
• A memory word at address 8 is the 32 bits at addresses 8,9,10,11
• Notation for 32-bit memory words: M[8]<31...0> := M[8] M[9] M[10] M[11] (concatenation)

Some more SRC Attributes

• All instructions are 32 bits long (1 word)
• All ALU instructions have three operands
• Memory is accessed only through load and store operations
• Only a few addressing modes are supported

SRC: Instruction Formats

Four types of instructions are supported: Type A, Type B, Type C, and shift instructions.

Encoding of the General Purpose Registers

A simple 5-bit encoding is used for fields ra, rb, and rc, representing any of the 32 registers. An exception is rb = 0, which means no operand.

Type A

Type A is used for only two instructions:

• nop (no operation), op-code = 0 — useful in pipelining
• stop (stop operation), op-code = 31 Both are 0-operand instructions.

Type B

Type B format includes three instructions using relative addressing mode:

• ldr (load register from memory using relative address), op-code = 2 📌 Example: ldr R3, 56 — loads R3 with contents of memory location M[PC+56]
• lar (load register with relative address), op-code = 6 📌 Example: lar R3, 56 — loads R3 with the relative address itself (PC+56)
• str (store register to memory using relative address), op-code = 4 📌 Example: str R8, 34 — stores R8 contents to M[PC+34]

The effective address is computed at run-time by adding a constant to the PC, making instructions ‘re-locatable’.

Type C

Type C format has three load/store instructions and three ALU instructions.

Load/Store instructions:

• ld (load register from memory), op-code = 1 📌 Example 1 (direct addressing): ld R3, 56 — loads R3 with M[56], rb field = 0 📌 Example 2 (indexed addressing): ld R3, 56(R5) — loads R3 with M[56+R[5]], rb ≠ 0
• la (load register with immediate data/address), op-code = 5 📌 Example 1 (immediate addressing): la R3, 56 — loads R3 with immediate value 56 📌 Example 2 (indexed addressing): la R3, 56(R5) — loads R3 with 56+R[5]
• st (store register contents to memory), op-code = 3 📌 Example 1 (direct): st R8, 34 — stores R8 contents to M[34] 📌 Example 2 (indexed): st R8, 34(R6) — stores R8 contents to M[34+R[6]]

ALU instructions:

• addi (immediate 2’s complement addition), op-code = 13 📌 Example: addi R3, R4, 56 → R[3] ← R[4] + 56 (rb field = R4)
• andi (immediate logical AND), op-code = 42 📌 Example: andi R3, R4, 56 — R3 loaded with logical AND of R4 and 56
• ori (immediate logical OR), op-code = 23 📌 Example: ori R3, R4, 56 — R3 loaded with logical OR of R4 and 56

Note about c2 field (17 bits):

• For direct addressing, only first 2¹⁶ bytes (or last 2¹⁶ if c2 is negative) can be accessed
• For la instruction, only constants with magnitudes less than ±2¹⁶ can be loaded
• During address calculation, sign extension to 32 bits must be performed before addition

Shift Instructions

Type C instructions, with modifications, may also be used for shift instructions. The four shift instructions are:

• shr (shift right), op-code = 26 📌 Example: shr R3, R4, 7 — shift R4 right 7 times into R3 (immediate)
• shra (arithmetic shift right), op-code = 27 📌 Example: shra R3, R4, 7 — shift R4 right 7 times into R3 (immediate)
• shl (shift left), op-code = 28 📌 Example: shl R8, R5, 6 — shift R5 left 6 times into R8 (immediate)
• shc (shift left circular), op-code = 29 📌 Example: shc R3, R4, 3 — shift R4 circular 3 times into R3 (immediate)

⭐ Key Takeaways

Execution time is the fundamental performance measure, calculated as IC × CPI × T. Benchmark programs like Whetstones (floating point) and Dhrystones (integer) are now considered obsolete due to size and optimization issues. SPEC provides a fair, standardized benchmark suite. The SRC processor has 32 general-purpose registers and uses big-endian byte storage with 32-bit instructions. There are four instruction formats: Type A (nop/stop), Type B (relative addressing with ldr, lar, str), Type C (direct/indexed load/store and ALU operations like addi, andi, ori), and shift instructions (shr, shra, shl, shc). The c2 field in Type C is 17 bits, requiring sign extension to 32 bits for address calculation.

🧠 Quick Revision Questions

1. What is the formula for Execution Time, and what do IC, CPI, and T represent?
2. Why are MIPS and MFLOPS considered problematic for comparing different processor architectures?
3. List three disadvantages of using Whetstones and Dhrystones as benchmark programs.
4. How does the SRC handle memory addressing in Type B instructions (ldr/lar/str), and what does "re-locatable" mean?
5. What is the difference between direct and indexed addressing modes in the SRC’s Type C load instruction (ld)? Provide an example of each.

📘 Lecture 4 — ISA and Instruction Formats

📖 Overview: This lecture introduces the Instruction Set Architecture (ISA) and instruction formats using the SRC (Simple RISC Computer) as an example machine. It covers SRC attributes, instruction types, addressing modes, and hand assembly, providing a foundation for understanding computer architecture design.

🗂️ Topics Covered

The lecture covers the SRC's attributes including registers, memory organization, and notation. It details four instruction formats (Types A through D) with their op-codes, operands, and addressing modes. The lecture includes coding examples for expression evaluation and extensive hand assembly demonstrations converting assembly language to machine code, along with assembler directives and memory mapping.

📝 Lecture Summary

Introduction to ISA and instruction formats

The lecture introduces the Instruction Set Architecture (ISA) as the interface between hardware and software, using the SRC (Simple RISC Computer) as an example machine. This example machine is simple enough to illustrate fundamentals while leaving out many details of a real computer.

An example computer: the SRC: “simple RISC computer”

SRC Introduction

The SRC is introduced as an example machine to facilitate understanding of various design steps and concepts in computer architecture. Though quite simple, it is complex enough to illustrate the fundamentals.

Attributes of the SRC

The SRC contains 32 General Purpose Registers: R0, R1... R31, each of size 32-bits. Two special purpose registers are included: Program Counter (PC) and Instruction Register (IR). Memory word size is 32 bits, memory space size is 2³² bytes, and memory organization is 2³² x 8 bits, meaning memory is byte aligned. Memory is accessed in 32 bit words (4 byte chunks), and Big-endian byte storage is used.

Programmer’s View of the SRC

The programmer sees 32, 32-bit registers as part of the CPU, the two additional CPU registers (PC & IR), and the main memory which is 2³² 1-byte cells.

SRC Notation

Key notation examples: R[3] means contents of register 3, M[8] means contents of memory location 8. A memory word at address 8 is defined as the 32 bits at addresses 8,9,10 and 11 in memory. A special notation for 32-bit memory words is M[8]<31...0>:=M[8] M[9] M[10] M[11] used for concatenation.

Some more SRC Attributes

All instructions are 32 bits long (instruction size is 1 word). All ALU instructions have three operands. The only way to access memory is through load and store operations. Only a few addressing modes are supported.

SRC: Instruction Formats

Four types of instructions (Type A, B, C, D) are supported by the SRC.

🔑 Definition — Encoding of General Purpose Registers: A simple 5-bit encoding where ra, rb, and rc are field "place-holders" that can represent any of the 32 registers. An exception is rb = 0; it does not mean register R0, rather it means no operand.

Type A

Type A is used for only two instructions: nop (No operation, op-code = 0, useful in pipelining) and stop (Stop operation, op-code = 31). Both are 0-operand instructions.

Type B

Type B format includes three instructions, all using relative addressing mode:

• ldr (load register from memory using relative address, op-code = 2): Example ldr R3, 56 loads register R3 with contents of memory location M[PC+56]
• lar (load register with relative address, op-code = 6): Example lar R3, 56 loads register R3 with the relative address itself (PC+56)
• str (store register to memory using relative address, op-code = 4): Example str R8, 34 stores register R8 contents to M[PC+34]

The effective address is computed at run-time by adding a constant to the PC, making instructions re-locatable.

Type C

Type C format has three load/store instructions plus three ALU instructions.

Load/Store instructions:

• ld (load register from memory, op-code = 1): Example ld R3, 56 loads R3 with M[56] (direct addressing, rb=0). Example ld R3, 56(R5) loads R3 with M[56+R[5]] (indexed addressing, rb≠0)
• la (load register with immediate value or address, op-code = 5): Example la R3, 56 loads R3 with immediate value 56 (immediate addressing). Example la R3, 56(R5) loads R3 with indexed address 56+R[5] (indexed addressing)
• st (store register contents to memory, op-code = 3): Example st R8, 34 stores R[8] to M[34] (direct addressing). Example st R8, 34(R6) stores R[8] to M[34+R[6]] (indexed addressing)

ALU instructions:

• addi (immediate 2's complement addition, op-code = 13): Example addi R3, R4, 56 performs R[3] ← R[4]+56
• andi (immediate logical AND, op-code = 21): Example andi R3, R4, 56 loads R3 with logical AND of R[4] and 56
• ori (immediate logical OR, op-code = 23): Example ori R3, R4, 56 loads R3 with logical OR of R[4] and 56

💡 Why this matters: Since the constant c2 field is 17 bits, for direct addressing mode only the first 2¹⁶ bytes of memory can be accessed (or last 2¹⁶ if c2 is negative). For la instruction, only constants with magnitudes less than ±2¹⁶ can be loaded. During address calculation using c2, sign extension to 32 bits must be performed before addition.

Shift instructions (modified Type C):

• shr (shift right, op-code = 26): Example shr R3, R4, 7 shifts R4 right 7 times into R3, shifting zeros in from left
• shra (arithmetic shift right, op-code = 27): Example shra R3, R4, 7 shifts R4 right 7 times into R3, copying msb into word on left
• shl (shift left, op-code = 28): Example shl R8, R5, 6 shifts R5 left 6 times into R8, shifting zeros in from right
• shc (shift left circular, op-code = 29): Example shc R3, R4, 3 shifts R4 circular 3 times into R3, value shifted out left placed back on right

Type D

Type D includes four ALU instructions, four register-based shift instructions, two logical instructions, and two branch instructions.

ALU instructions (register addressing):

• add (2's complement register addition, op-code = 12): Example add R3, R5, R6 stores R[5]+R[6] in R3
• sub (2's complement register subtraction, op-code = 14): Example sub R3, R5, R6 stores R[5]-R[6] in R3
• and (logical AND between registers, op-code = 20): Example and R8, R3, R4 stores logical AND of R3 and R4 in R8
• or (logical OR between registers, op-code = 22): Example or R8, R3, R4 loads R8 with logical OR of R3 and R4

Register-based shift instructions (register addressing):

• shr (shift right using register rc, op-code = 26): Example shr R3, R4, R5 shifts R4 right into R3 using number in R5
• shra (arithmetic shift right using register rc, op-code = 27): Example shra R3, R4, R5 shifts R4 right using R5
• shl (shift left using register rc, op-code = 28): Example shl R8, R5, R6 shifts R5 left into R8 using number in R6
• shc (shift left circular using register rc, op-code = 29): Example shc R3, R4, R6 shifts R4 circular into R3 using value in R6

Logical instructions (modified Type D, 2-address format):

• neg (2's complement negation, op-code = 15): Example neg R3, R4 negates R4 and stores in R3
• not (1's complement, op-code = 24): Example not R3, R4 logically inverts R4 and stores in R3

Branch instructions (modified Type D, register addressing):

• br (branch to address in rb depending on condition in rc, op-code = 8): Branches based on five conditions:

  • brzr R3, R4 — Branch to address in R3 if R4 == 0
  • brnz R3, R4 — Branch to address in R3 if R4 ≠ 0
  • brpl R3, R4 — Branch to address in R3 if R4 ≥ 0
  • brmi R3, R4 — Branch to address in R3 if R4 < 0
  • br R3, R4 — Unconditional branch to address in R3

• brl (branch to address in rb depending on condition in rc, copies PC to ra before branching, op-code = 9):

  • brlzr R1, R3, R4 — R1 stores PC, then branch to R3 if R4 == 0
  • brlnz R1, R3, R4 — R1 stores PC, then branch to R3 if R4 ≠ 0
  • brlpl R1, R3, R4 — R1 stores PC, then branch to R3 if R4 ≥ 0
  • brlmi R1, R3, R4 — R1 stores PC, then branch to R3 if R4 < 0
  • brl R1, R3, R4 — R1 stores PC, then ALWAYS branch to R3
  • brlnv R1, R3, R4 — R1 stores PC, but branch NEVER taken

The bits <2...0> are used for specifying the condition, with condition codes serving as op code extensions.

Examples

Example 1: Expression Evaluation Write an SRC assembly program to evaluate: z = 4(a+b) – 16(c+58), without changing source operands.

Solution A (using shift for multiply since SRC has no multiply instruction):

ld R1, c          ; c is a label used for a memory location
addi R3, R1, 58   ; R3 contains (c+58)
shl R7, R3, 4     ; R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5    ; R6 contains (a+b)
shl R8, R6, 2     ; R8 contains 4(a+b)
sub R9, R8, R7    ; the result is in R9
st R9, z          ; store the result in memory location z

Memory labels a, b, c, z are defined using assembler directives like .dw or .db. A semicolon ';' is used for comments.

Example 2: Hand Assembly Convert the SRC assembly program to machine language.

Source program with directives:

.ORG 200          ; start the next line at address 200
a: .DW 1          ; reserve one word for label a at address 200
b: .DW 1          ; reserve a word for b at address 204
c: .DW 1          ; reserve a word for c at address 208
z: .DW 1          ; reserve one word for result at address 212

.ORG 400          ; start the code at address 400

ld R1, c          ; c is a label used for a memory location
addi R3, R1, 58   ; R3 contains (c+58)
shl R7, R3, 4     ; R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5    ; R6 contains (a+b)
shl R8, R6, 2     ; R8 contains 4(a+b)
sub R9, R8, R7    ; the result is in R9
st R9, z          ; store the result in memory location z

Hand Assembly Process for ld R1, c (Type C, rb missing):

1. Op-code for ld = 00001
2. Register code for R1 = 00001
3. rb field missing, place zeros: 00000
4. c is at address 208, 17-bit binary = 00000 0000 1101 0000
5. Complete instruction: 00001 00001 00000 00000 0000 1101 0000
6. Hexadecimal: 0 8 4 0 0 0 D 0 h

For addi R3, R1, 58 (Type C):

1. Op-code for addi = 01101
2. Register codes: R3 = 00011, R1 = 00001
3. Immediate data 58 in binary: 00000 0000 0011 1010
4. Complete: 01101 00011 00001 00000 0000 0011 1010
5. Hexadecimal: 6 8 C 2 0 0 3 A h

For shl R7, R3, 4 (Type C):

1. Op-code for shl = 11100
2. Register codes: R7 = 00111, R3 = 00011
3. Immediate data 4 in binary: 00000 0000 0000 0100
4. Complete: 11100 00111 00011 00000 0000 0000 0100
5. Hexadecimal: E1C60004

For ld R4, a (Type C, rb missing):

1. Op-code for ld = 00001
2. Register code for R4 = 00100
3. rb field missing: 00000
4. a at address 200, 17-bit binary: 00000 0000 1100 1000
5. Complete: 00001 00100 00000 00000 0000 1100 1000
6. Hexadecimal: 0 9 0 0 0 0 C 8 h

For ld R5, b (Type C, rb missing):

1. Op-code = 00001, R5 = 00101
2. rb field missing: 00000
3. b at address 204, 17-bit binary: 00000 0000 1100 1100
4. Complete: 00001 00101 00000 00000 0000 1100 1100
5. Hexadecimal: 0 9 4 0 0 0 C C h

For add R6, R4, R5 (Type D, constant missing):

1. Op-code for add = 01100
2. Register codes: R6 = 00110, R4 = 00100, R5 = 00101
3. 12-bit constant unused: 0000 0000 0000
4. Complete: 01100 00110 00100 00101 0000 0000 0000
5. Hexadecimal: 6 1 8 8 5 0 0 0 h

For shl R8, R6, 2 (Type C, rc missing):

1. Op-code for shl = 11100
2. Register codes: R8 = 01000, R6 = 00110
3. Immediate data 2 in binary: 00000 0000 0000 0010
4. Complete: 11100 01000 00110 00000 0000 0000 0010
5. Hexadecimal: E 2 0 C 0 0 0 2

For sub R9, R7, R8 (Type D):

1. Op-code for sub = 01110
2. Register codes: R9 = 01001, R7 = 00111, R8 = 01000
3. 12-bit constant unused: 0000 0000 0000
4. Complete: 01110 01001 00111 01000 0000 0000 0000
5. Hexadecimal: 7 2 4 E 8 0 0 0 h

For st R9, z (Type C, rb missing):

1. Op-code for st = 00011
2. Register code for R9 = 01001
3. rb field missing: 00000
4. z at address 212, 17-bit binary: 00000 0000 1101 0100
5. Complete: 00011 01001 00000 00000 0000 1101 0100
6. Hexadecimal: 1 A 4 0 0 0 D 4 h

Memory Map (byte-aligned representation):

Assembler Directives

Assembler directives (pseudo op-codes) are commands to the assembler to direct the assembly process. Key directives used:

• .ORG — Specifies starting address for code/variables (e.g., .ORG 200)
• .DW — Reserves one word in memory for a label (e.g., a: .DW 1)
• Most assemblers require source files saved with .asm extension

⭐ Key Takeaways

Students must understand the four SRC instruction formats (Types A, B, C, D) and their op-codes, addressing modes, and operand structures. The 5-bit register encoding (R0-R31) and the special meaning of rb=0 (no operand) are critical. Hand assembly requires careful mapping of op-codes, register codes, and immediate/address values into the correct bit fields, with sign extension for negative constants. Memory organization uses byte alignment with 32-bit words and big-endian storage. The relationship between assembly instructions, machine code (binary and hexadecimal), and memory addresses must be mastered for understanding computer architecture fundamentals.

🧠 Quick Revision Questions

1. What are the four instruction types in the SRC, and what is each used for?
2. How many general purpose registers does the SRC have, and what is the bit width of each?
3. What is the difference between the ld and ldr instructions in terms of addressing mode?
4. How would you encode the instruction add R5, R2, R3 into machine language (binary and hexadecimal)?
5. What is the purpose of the .ORG and .DW assembler directives?

📘 Lecture 5 — Description of SRC in RTL

📖 Overview: This lecture introduces how to describe the SRC (Simple 'RISC' Computer) using Register Transfer Language (RTL). It covers both behavioral and structural descriptions, explains how to specify registers and fields, and details the instruction interpretation and execution phases of the fetch-execute cycle.

🗂️ Topics Covered

The lecture covers reverse assembly of machine language instructions into SRC assembly, the definition and use of RTL for behavioral and structural descriptions, specification of static properties including registers and instruction fields, dynamic properties including effective address calculations, and detailed description of instruction interpretation (fetch) and execution phases for all instruction types including load-store, branch, arithmetic/logical, shift, and miscellaneous instructions.

📝 Lecture Summary

Reverse Assembly

Reverse assembly is the process of converting machine language instructions back into their equivalent SRC assembly language instructions. The process involves writing the hexadecimal instruction in binary, examining the first five bits to determine the op-code and corresponding mnemonic, and then interpreting the remaining fields based on the instruction format.

🔑 Definition — Reverse Assembly: The process of finding the equivalent SRC assembly language instruction from a given machine language instruction.

📌 Example: Reverse assemble 68C2003A h

• Step 1: Convert to binary: 0110 1000 1100 0010 0000 0000 0011 1010 b
• Step 2: First 5 bits = 01101 b = 13 d → addi (add immediate)
• Step 3: This uses Type C format: op-code (01101), ra field (00011=R3), rb field (00001=R1), 17-bit c1 field (00000 0000 0011 1010 = 3A h = 58 d)
• Result: addi R3, R1, 58

📌 Example: E1C60004 h → 1110 0001 1100 0110 0000 0000 0000 0100 b → op=11100=28 d → shl (shift left) → Type C format → shl R3, R1, 4

📌 Example: 61885000 h → 0110 0001 1000 1000 0101 0000 0000 0000 b → op=01100=12 d → add → Type C format → add R3, R1, R0

📌 Example: 724E8000 h → 0111 0010 0100 1110 1000 0000 0000 0000 b → op=01110=14 d → sub → sub R1, R2, R3

📌 Example: 1A4000D4 h → 0001 1010 0100 0000 0000 0000 1101 0100 b → op=00011=3 d → st (store) → Type C → st R1, R0, D4h

📌 Example: 084000D0 h → 0000 1000 0100 0000 0000 0000 1101 0000 b → op=00001=1 d → ld (load) → ld R1, R0, D0h

💡 Why this matters: Reverse assembly is essential for debugging and understanding machine code output from assemblers.

Using RTL to Describe the SRC

RTL stands for Register Transfer Language, which provides a formal way for describing the behavior and structure of a computer. RTL facilitates the design process by providing a precise, mathematical representation of functionality.

Behavioral RTL describes the 'functionality' of the machine only — what the machine does. Structural RTL describes the 'hardware implementation' of the machine — how the functionality is implemented. In computer design, a top-down approach is adopted: starting with behavioral description, then breaking down into modules, until we can define, design, and implement the structure of individual modules.

Using RTL to Describe Static Properties of the SRC

Specifying Registers: The format used is Register Name<register bits>. For example, IR<31..0> means bits 31 to 0 of a 32-bit register named "IR" (Instruction Register).

The := operator is the naming operator used to 'name' registers or parts of registers. It does not create a new register; it just generates another name or "alias" for an already existing register or part of a register.

🔑 Definition — Naming Operator (:=): Creates an alias for an existing register or part of a register. For example, Op<4..0> := IR<31..27> means the five most significant bits of IR will be called op.

Fields in the SRC Instruction

Using RTL, the various fields of an SRC instruction are specified:

• op<4..0> := IR<31..27>; operation code field (5 most significant bits)
• ra<4..0> := IR<26..22>; target register field (where the result is stored)
• rb<4..0> := IR<21..17>; operand, address index, or branch target register
• rc<4..0> := IR<16..12>; second operand, conditional test, or shift count register
• c1<21..0> := IR<21..0>; long displacement field (22 bits)
• c2<16..0> := IR<16..0>; short displacement or immediate field (17 bits)
• c3<11..0> := IR<11..0>; count or modifier field (12 bits)

Note: There is overlap of fields. The fields are distinguished in a particular instruction depending on the operation.

Describing Processor State Using RTL

The following registers and bits together form the processor state set:

• PC<31..0>; program counter (holds memory address of next instruction)
• IR<31..0>; instruction register (holds current instruction)
• Run; one bit run/halt indicator
• Strt; start signal
• R [0..31]<31..0>; 32, 32-bit general purpose registers

Difference Between "," and ";" in RTL

Statements separated by a "," take place during the same clock pulse — the order of execution does not matter. Statements separated by a ";" take place on successive clock pulses — the one on the left must complete before the one on the right starts.

In statements separated by ",", all right-hand sides of Register Transfers are evaluated before any left-hand side is modified.

Using RTL to Describe Dynamic Properties of the SRC

Conditional expressions can be specified through RTL:

🔑 Example: (op=14) : R [ra] ← R [rb] - R[rc]; The ← operator is the RTL assignment operator. ; is the termination operator. This means: "IF the op field equals 14, THEN calculate the difference of the value in register rb and register rc, and store the result in register ra."

Effective Address Calculations in RTL

Displacement address (calculated at runtime): disp<31..0> := ((rb=0) : c2<16..0> {sign extend}, (rb≠0) : R [rb] + c2<16..0> {sign extend})

If rb=0, just use the displacement value (sign extended). If rb≠0, add the register value to the displacement. The comma separates disjoint conditions — only one action will be performed at a time.

Relative address: rel<31..0> := PC<31..0> + c1<21..0> {sign extend}

Range of memory addresses:

• Direct addressing (displacement with rb=0):
  • If c2<16>=0 (positive): addresses from 00000000h to 0000FFFFh
  • If c2<16>=1 (negative): addresses from FFFF0000h to FFFFFFFFh
• Relative addressing: Largest positive c1 value is 2²¹-1, most negative is -2²¹, so addresses up to 2²¹-1 forward and 2²¹ backward from current PC

Instruction Interpretation (Fetch Operation Using RTL)

The action performed for all instructions before they are decoded is called instruction interpretation.

🔑 Formula:

instruction_Fetch := (
    !Run & Strt: Run ← 1 ; instruction_Fetch
    Run : (IR ← M [PC], PC ← PC + 4; instruction_Execution)
);

If the machine is not running (!Run) AND start (Strt) becomes true, Run is set to 1. If running, the instruction register is loaded with the instruction at M[PC] and PC is incremented by 4 simultaneously.

Instruction Execution (Execute Operation Using RTL)

Once the instruction is fetched and PC incremented, execution starts. iF denotes instruction fetch and iE denotes instruction execution.

🔑 Formula:

iE:= (
    (op<4..0>=1) : R [ra] ← M [disp],
    (op<4..0>=2) : R [ra] ← M [rel],
    ...
    (op<4..0>=31) : Run ← 0,); iF);

One statement is executed depending on the condition met, then iF is invoked again — forming the fetch-execute cycle.

Load-Store Instructions

• ld (op=1): R [ra] ← M [disp] — Load register using displacement address
• ldr (op=2): R [ra] ← M [rel] — Load register using relative address
• st (op=3): M [disp] ← R [ra] — Store register to displacement address
• str (op=4): M[rel] ← R[ra] — Store register to relative address
• la (op=5): R [ra] ← disp — Load displacement address into register
• lar (op=6): R [ra] ← rel — Load relative address into register

Branch Instructions

• br (op=8): (cond : PC ← R [rb]) — Conditional branch to target in rb
• brl (op=9): (R [ra] ← PC, cond : (PC ← R [rb]) ) — Branch and link: store PC in ra, then branch

The cond conditions depend on c3<2..0>:

• c3=0: 0 — never branch
• c3=1: 1 — always branch
• c3=2: R [rc]=0 — branch if register zero
• c3=3: R [rc] ≠ 0 — branch if register nonzero
• c3=4: R [rc]<31>=0 — branch if positive or zero
• c3=5: R [rc]<31>=1 — branch if negative

Arithmetic and Logical Instructions

• add (op=12): R [ra] ← R [rb] + R [rc]
• addi (op=13): R [ra] ← R [rb] + c2<16..0> {sign extend}
• sub (op=14): R [ra] ← R [rb] – R [rc]
• neg (op=15): R [ra] ← -R [rc]
• and (op=20): R [ra] ← R [rb] & R [rc]
• andi (op=21): R [ra] ← R [rb] & c2<16..0> {sign extend}
• or (op=22): R [ra] ← R [rb] ~ R [rc]
• ori (op=23): R [ra] ← R [rb] ~ c2<16..0> {sign extend}
• not (op=24): R [ra] ← ¬R [rc]

Shift Instructions

• shr (op=26): R [ra]<31..0> ← (n α 0) © R [rb] <31..n> — Shift right n bits, fill with 0s
• shra (op=27): R [ra]<31..0> ← (n α R [rb] <31>) © R [rb] <31..n> — Shift right arithmetic (fill with sign bit)
• shl (op=28): R [ra]<31..0> ← R [rb] <31-n..0> © (n α 0) — Shift left n bits
• shc (op=29): R [ra]<31..0> ← R [rb] <31-n..0> © R [rb]<31..32-n> — Shift circular (bits rotate)

Where n := ((c3<4..0>=0) : R [rc], (c3<4..0>!=0) : c3<4..0>)

Notation: α means replication, © means concatenation

Miscellaneous Instructions

• nop (op=0): No operation — used as a stall in pipelining
• stop (op=31): Run ← 0 — Halt the processor

Flow Diagram

The flow diagram is the symbolic representation of the fetch-execute cycle. The top block indicates instruction fetch, then instruction decode by looking at the first 5 bits for the op-code (0 to 31). Depending on the op-code, appropriate processing takes place, then the cycle returns to fetch the next instruction until op-code 31 halts the system.

⭐ Key Takeaways

The most critical concepts from this lecture are: (1) RTL uses the := naming operator to create aliases for register fields, the ← assignment operator for data transfers, , for concurrent operations within one clock, and ; for sequential operations across clocks; (2) the instruction format consists of op (bits 31-27), ra (26-22), rb (21-17), rc (16-12), and various displacement fields (c1, c2, c3) with overlapping bits distinguished by the operation; (3) the fetch-execute cycle is defined as iF fetching IR←M[PC] and PC←PC+4 concurrently, then iE executing one of 31 disjoint conditional operations based on the op-code; (4) effective address calculations include displacement addressing (disp) and relative addressing (rel) with specific memory address ranges; and (5) branch instructions use six conditional tests specified by the c3 field including never, always, zero, nonzero, positive/zero, and negative.

🧠 Quick Revision Questions

1. What is the difference between the "," and ";" operators in RTL, and how do they affect execution timing?
2. Describe the step-by-step process for reverse assembling the machine instruction 724E8000h into SRC assembly language.
3. Write the RTL expressions for the op, ra, rb, and rc fields and identify which bits of the IR register each field occupies.
4. Explain how the displacement address (disp) is calculated in RTL and describe the difference when rb=0 versus rb≠0.
5. What are the six possible branch conditions specified by the c3 field, and what does each condition test?

📘 Lecture 6 — RTL Using Digital Logic Circuits

📖 Overview: This lecture continues the discussion of behavioral RTL for describing the SRC processor, covering the complete instruction set including load-store, branch, arithmetic/logical, shift, and miscellaneous instructions. It then transitions into the hardware implementation of register transfers using digital logic circuits, reviewing basic components like D flip-flops, registers, multiplexers, and tri-state buffers, and demonstrating how these are used to build buses, register files, and functional units like adders and barrel shifters.

🗂️ Topics Covered

The lecture begins by completing the behavioral RTL description of the SRC’s instruction set, detailing each instruction class (load-store, branch, arithmetic/logical, shift, miscellaneous). The second major section covers implementing register transfers with digital logic, starting with a review of fundamental components (D flip-flops, n-bit registers, n-to-1 multiplexers, tri-state buffers), then building up to simple conditional transfers, two-way transfers, multiple register connections, bus architectures, register file implementation, register transfers with mathematical operations (using adders), and finally the barrel shifter for implementing shift operations.

📝 Lecture Summary

Using behavioral RTL to Describe the SRC (continued)

Once the instruction is fetched and the PC is incremented, execution of the instruction starts. In the following discussion, we denote instruction fetch by “iF” and instruction execution by “iE”. Instruction execution can be described by a long list of conditional operations which are inherently “disjoint”. Only one of these statements is executed depending on the condition met, and then the instruction fetch statement (iF) is invoked again at the end of the list of concurrent statements. Thus, instruction fetch (iF) and instruction execution statements invoke each other in a loop, which represents the fetch-execute cycle of the SRC.

🔑 Definition — fetch-execute cycle: The continuous loop where the processor fetches an instruction from memory and then executes it, repeating indefinitely until a halt instruction is encountered.

Load-Store Instructions

(op<4..0>= 1) : R [ra] ← M [disp] — load register (ld): This instruction loads a register using a displacement address specified by the instruction, i.e., the contents of the memory at the address 'disp' are placed in the register R[ra].

(op<4..0>= 2) : R [ra] ← M [rel] — load register relative (ldr): If the operation field 'op' of the instruction decoded is 2, the instruction that is executed is loading a register (target address of this register is specified by the field ra) with memory contents at a relative address, 'rel'.

(op<4..0>= 3) : M [disp] ← R [ra] — store register (st): If the op-code is 3, the contents of the register specified by address ra are stored back to the memory at a displacement location 'disp'.

(op<4..0>= 4) : M[rel] ← R[ra] — store register relative (str): If the op-code is 4, the contents of the register specified by the target register address ra are stored back to the memory at a relative address location 'rel'.

(op<4..0>= 5) : R [ra] ← disp — load displacement address (la): For op-code 5, the displacement address disp is loaded to the register R (specified by the target register address ra).

(op<4..0>= 6) : R [ra] ← rel — load relative address (lar): For op-code 6, the relative address rel is loaded to the register R (specified by the target register address ra).

Branch Instructions

(op<4..0>= 8) : (cond : PC ← R [rb]) — conditional branch (br): If the op-code is 8, a conditional branch is taken, that is, the program counter is set to the target instruction address specified by rb, if the condition 'cond' is true.

(op<4..0>= 9) : (R [ra] ← PC, cond : (PC ← R [rb]) ) — branch and link (brl): If the op field is 9, the branch and link instruction is executed, i.e., the contents of the program counter are stored in a register specified by ra field (so control can be returned to it later), and then the conditional branch is taken to a branch target address specified by rb. The branch and link instruction is useful for returning control to the calling program after a procedure call returns.

The conditions that these 'conditional' branches depend on are specified by the field c3 that has 3 bits. When c3<2..0> is equal to one of these values, we substitute the expression on the right-hand side of the ":" in place of cond.

cond := (

• c3<2..0>=0 : 0 — never: If the c3 field is 0, the branch is never taken.
• c3<2..0>=1 : 1 — always: If the field is 1, branch is taken.
• c3<2..0>=2 : R [rc]=0 — if register is zero: If c3 = 2, a branch is taken if the register rc = 0.
• c3<2..0>=3 : R [rc] ≠ 0 — if register is nonzero: If c3 = 3, a branch is taken if the register rc is not equal to 0.
• c3<2..0>=4 : R [rc]<31>=0 — if positive or zero: If c3 is 4, a branch is taken if the register value in the register specified by rc is greater than or equal to 0.
• c3<2..0>=5 : R [rc]<31>=1 — if negative: If c3 = 5, a branch is taken if the value stored in the register specified by rc is negative.

Arithmetic and Logical Instructions

(op<4..0>=12) : R [ra] ← R [rb] + R [rc]: If the op-code is 12, the contents of the registers rb and rc are added, and the result is stored in the register ra.

(op<4..0>=13) : R [ra] ← R [rb] + c2<16..0> {sign extended}: If the op-code is 13, the content of the register rb is added with the immediate data in the field c2, and the result is stored in the register ra.

(op<4..0>=14) : R [ra] ← R [rb] – R [rc]: If the op-code is 14, the content of the register rc is subtracted from that of rb, and the result is stored in ra.

(op<4..0>=15) : R [ra] ← -R [rc]: If the op-code is 15, the content of the register rc is negated, and the result is stored in ra.

(op<4..0>=20) : R [ra] ← R [rb] & R [rc]: If the op field equals 20, logical AND of the contents of the registers rb and rc is obtained, and the result is stored in register ra.

(op<4..0>=21) : R [ra] ← R [rb] & c2<16..0> {sign extended}: If the op field equals 21, logical AND of the content of the registers rb and the immediate data in the field c2 is obtained, and the result is stored in register ra.

(op<4..0>=22) : R [ra] ← R [rb] ~ R [rc]: If the op field equals 22, logical OR of the contents of the registers rb and rc is obtained, and the result is stored in register ra.

(op<4..0>=23) : R [ra] ← R [rb] ~ c2<16..0> {sign extended}: If the op field equals 23, logical OR of the content of the registers rb and the immediate data in the field c2 is obtained, and the result is stored in register ra.

(op<4..0>=24) : R [ra] ← !R [rc]: If the op-code equals 24, the logical NOT of the content of the register rc is obtained, and the result is stored in ra.

Shift Instructions

(op<4..0>=26): R [ra]<31..0 > ← (n α 0) © R [rb] <31..n> — shift right logical: If the op-code is 26, the contents of the register rb are shifted right n bits times. The bits that are shifted out of the register are discarded. 0s are added in their place, i.e., n number of 0s is added (or concatenated) with the register contents. The result is copied to the register ra.

(op<4..0>=27) : R [ra]<31..0 > ← (n α R [rb] <31>) © R [rb] <31..n> — shift right arithmetic: For op-code 27, shift arithmetic operation is carried out. In this operation, the contents of the register rb are shifted right n times, with the most significant bit, i.e., bit 31, of the register rb added in their place. The result is copied to the register ra.

(op<4..0>=28) : R [ra]<31..0 > ← R [rb] <31-n..0> © (n α 0) — shift left logical: For op-code 28, the contents of the register rb are shifted left n bits times, similar to the shift right instruction. The result is copied to the register ra.

(op<4..0>=29) : R [ra]<31..0 > ← R [rb] <31-n..0> © R [rb]<31..32-n > — rotate left (circular): The instruction corresponding to op-code 29 is the shift circular instruction. The contents of the register rb are shifted left n times; however, the bits that move out of the register in the shift process are not discarded; instead, these are shifted in from the other end (a circular shifting). The result is stored in register ra.

where n := ((c3<4..0>=0) : R [rc], (c3<4..0>!=0) : c3 <4..0> )

📌 Notation: α means replication; © means concatenation

Miscellaneous Instructions

(op<4..0>= 0) — No operation (nop): If the op-code is 0, no operation is carried out for that clock period. This instruction is used as a stall in pipelining.

(op<4..0>= 31) : Run ← 0 — Halt the processor (Stop): If the op-code is 31, run is set to 0, that is, the processor stops execution.

After one of these disjoint instructions is executed, iF, i.e., instruction Fetch, is carried out once again, and so the fetch-execute cycle continues.

Implementing Register Transfers using Digital Logic Circuits

We have studied the register transfers in the previous sections and how they help in implementing assembly language. In this section we will review how the basic digital logic circuits are used to implement instructions register transfers. The topics covered include:

1. A brief (and necessary) review of logic circuits
2. Implementing simple register transfers
3. Register file implementation using a bus
4. Implementing register transfers with mathematical operations
5. The Barrel Shifter
6. Implementing shift operations

Review of logic circuits

The topics reviewed in this section include: the basic D flip-flop, the n-bit register, the n-to-1 multiplexer, and tri-state buffers.

The basic D flip-flop

A flip-flop is a bi-stable device capable of storing one bit of information. Therefore, flip-flops are used as the building blocks of a computer's memory as well as CPU registers. The most common type, the D flip-flop, is set (i.e., stores a 1) when the data input is high on the leading (also called the positive) edge of the clock; it is reset (i.e., the flip-flop stores a 0) when the data input is 0 on the leading edge of the clock. The clear input will reset the flip-flop on a low input.

The n-bit register

An n-bit register can be formed by grouping n flip-flops together. A register is a device in which a group of flip-flops operate synchronously. A register is useful for storing binary data, as each flip-flop can store one bit. The clock input of the flip-flops is grouped together, as is the enable input. Using the input lines, a binary number can be stored in the register by applying the corresponding logic level to each of the flip-flops simultaneously at the positive edge of the clock. For a 4-bit register, In0 through In3 are the four input lines, Out0 through Out3 are the four output lines, Clk is the clock input, and En is the enable line. The enable input has to be high if the number is to be stored into the register.

The n-to-1 multiplexer

A multiplexer is a device constructed through combinational logic, which takes n inputs and transfers one of them as the output at a time. The input that is selected as the output depends on the selection lines, also called the control input lines. For an n-to-1 multiplexer, there are n input lines, log₂n control lines, and 1 output line.

📌 Example: For a 4-to-1 multiplexer, there are 4 input lines (lines 0 through 3), and 2 select lines (since log₂4 = 2). To transfer the input of line 3 to the output, apply the binary number 11 on the select lines (as the binary number 11 represents the decimal number 3). The output of the multiplexer will then be the input on line 3.

Tri-state buffers

The tri-state buffer, also called the three-state buffer, has a single input, a single output, and an enable line. The input is connected to the output only if it is enabled through the enable line; otherwise, it gives a high impedance output, i.e., it is tri-stated, or electrically disconnected from the input. These buffers are available both in the inverting and the non-inverting form. The inverting tri-state buffers output the 'inverted' input when they are enabled. When the enable input (or the control input) c is low (0), the output is high impedance Z.

📌 Example: In a 4-bit tri-state buffer unit, if we apply a high on input 3 and 2, and a low on input 1 and 0, we get the output 1100, only when the enable input is high.

Implementing simple register transfers

We now build on our knowledge of the primitive logic circuits to understand how register transfers are implemented. This section covers: simple conditional transfer, the concept of control signals, two-way transfers, connecting multiple registers, buses, and bus implementations.

Simple conditional transfer

In a simple conditional transfer, a condition is checked, and if it is true, the register transfer takes place. Formally, a conditional transfer is represented as:

Cond: RD ← RS

This means that if the condition 'Cond' is true, the contents of the register named RS (the source register) are copied to the register RD (the destination register). The output of the source register RS is connected to the input of the destination register RD. The transfer will not take place unless the enable input of the destination register is activated. The 'transfer' is being controlled by the enable line (or the control signal). The condition is, in general, a Boolean expression.

Two-way transfers

In one-way transfer, we could only copy the contents of RS to RD if the condition was met. To achieve two-way transfers, we must also provide a path from the output of the register RD to the input of register RS, enabling us to implement:

• Cond1: RD ← RS
• Cond2: RS ← RD

Connecting multiple registers

To connect more than two registers, one may argue that a connection between the input and output of each be provided. For a scenario with 5 registers, an m-bit register requires two connections of m-wires each. Hence, five m-bit registers in a point-to-point scheme require 20 connections, each with m wires. In general, n registers in a point-to-point scheme require n(n-1) connections. This solution does not scale well for a large number of registers. The solution to this problem is the use of a bus architecture.

Buses

A bus is a device that provides a shared data path to a number of devices that are connected to it via a 'set of wires' or a 'set of conductors'. The modern computer systems extensively employ the bus architecture. Control signals are needed to decide which two entities communicate using the shared medium, i.e., the bus, at any given time. These control signals can be open-collector gate-based, tri-state buffer-based, or they can be implemented using multiplexers.

Register file implementation using the bus architecture

A number of registers can be interconnected to form a register file through the use of a bus. For eight 4-bit registers (R0, R1, ..., R7) interconnected through a 4-bit bus using 4-bit tri-state buffer units, the contents of a particular register can be transferred onto the bus by applying a logical high input on the enable of the corresponding tri-state buffer. For instance, R1out can be used to enable the tri-state buffers of the register R1, and in turn transfer the contents of the register onto the bus. Once the contents of a particular register are on the bus, the contents may be transferred, or read into any other register. More than one register may be written in this manner; however, only one register can write its value on the bus at a given time.

Implementing register transfers with mathematical operations

Frequently we encounter register transfers with mathematical operations, such as (opc=1): R4 ← R3 + R2. These mathematical operations may be achieved by introducing appropriate combinational logic. This operation can be implemented in hardware by including a 4-bit adder with the register files connected through the bus. Two more registers are included: one for holding one of the operands (register A), and the other for holding the result (register C) before it is transferred to the destination register.

📌 Example: Steps for the conditional mathematical transfer (opc=1): R4 ← R3 + R2:

1. If the condition opc = 1 is met, the contents of R3 are transferred to the temporary register A through the bus. This is done by activating R3out (loading R3 onto the bus) and simultaneously applying a logical high input to LA (loading the register A).
2. Enable R2out to load the contents of register R2 onto the bus. The output of register A is one input to the 4-bit adder; the other input to the adder is the bus itself. As the contents of register R2 are loaded onto the bus, both operands are available to the adder. The output can then be stored to the register C by enabling its write (applying a high input to LC).
3. Store the resultant number in the destination register R4. This is done by enabling Cout (writing the number onto the bus) and then enabling the read of register R4 by activating the control signal LR4.

💡 Why this matters: This example demonstrates the fundamental process by which the CPU executes an arithmetic instruction — moving operands onto a bus, through combinational logic (the adder), and into a temporary register before the final store.

The barrel shifter

Shift operations are frequently used operations, as shifts can be used for the implementation of multiplication and division. A bi-directional shift register with a parallel load capability can be used to perform shift operations. However, the delays in such structures are dependent on the number of shifts to be performed (e.g., a 9-bit shift requires nine clock periods, as one shift is performed per clock cycle). This is not an optimal solution.

The barrel shifter is an alternative, with any number of shifts accomplished during a single clock period. Barrel shifters are constructed by using multiplexers. An n-bit barrel shifter is a combinational circuit implemented using n multiplexers. The barrel provides a shifted copy of the input data at its output. Control inputs are provided to specify the number of times the input data is to be shifted.

📌 Example: For a barrel shifter that shifts right the input data, the number of shifts depends on the bit pattern applied on the control inputs S0, S1. To apply a single shift, the control signal is 01 on (S1, S0), which is the binary equivalent of the decimal number 1. To apply 2 shifts, control signal 10 is applied. A control input of 11 shifts the number 3 places to the right.

Implementing shift operations

The shift functionality can be incorporated into the register file circuit with the bus architecture by introducing the barrel shifter.

📌 Example: To perform the operation R4 ← ror R3 (2 times):

1. Activate R3out, nb1, and LC. Activating R3out loads the contents of register R3 onto the bus. Since the bus is directly connected to the input of the barrel shifter, this number is applied to the input side. nb1 and nb0 are the barrel shifter's control lines for specifying the number of shifts. Applying a high input to nb1 and a low input to nb0 will shift the number two places to the right. Activating LC will load the shifted output of the barrel shifter into register C.
2. Transfer the contents of register C to register R4. This is done by activating the control Cout, which will load the contents of register C onto the data bus, and by activating the control LR4, which will let the contents of the bus be written to register R4.

⭐ Key Takeaways

The SRC processor's instruction set is described using behavioral RTL as a list of disjoint conditional operations within the fetch-execute cycle. Each instruction class (load-store, branch, arithmetic/logical, shift, and miscellaneous) has a specific opcode and RTL representation. Hardware implementation of register transfers relies on fundamental digital logic components: D flip-flops (for storage), n-bit registers, multiplexers (for selection), and tri-state buffers (for bus access). The bus architecture is critical for scaling register interconnections, replacing the impractical point-to-point scheme. Complex operations like addition and shifting are implemented by introducing combinational logic (adders) and specialized circuits (barrel shifters) into the bus-based register file, with control signals managing the sequence of data movement.

🧠 Quick Revision Questions

1. What does the RTL statement (op<4..0>=12) : R [ra] ← R [rb] + R [rc] mean in terms of the instruction it represents and the registers involved?
2. How does a barrel shifter differ from a traditional shift register in terms of performance, and what is the key advantage?
3. Why is a bus architecture preferred over a point-to-point connection scheme when connecting multiple registers?
4. What is the purpose of the tri-state buffer in a bus-based register file, and what happens when the enable input is low?
5. In the implementation of (opc=1): R4 ← R3 + R2, what are the three steps and which control signals are activated in each step?

📘 Lecture 7 — Design Process for ISA of FALCON-A

📖 Overview: This lecture outlines the systematic thinking process for designing an Instruction Set Architecture (ISA) by walking through each step of creating the ISA for a new processor called FALCON-A. It covers the key elements that define any ISA and introduces the programmer's view of the FALCON-A processor, which will serve as a teaching aid throughout the course.

🗂️ Topics Covered

The lecture covers the three key components that define any ISA: the operations the processor can execute, data access mode for operands, and representation of operations in memory. It then details eight specific steps for designing the FALCON-A ISA, including selecting instructions, choosing mnemonics, allocating op-code bits, assigning op-codes, determining operand types and formats, designing memory organization, specifying memory access instructions, and selecting addressing modes. The lecture concludes with an introduction to the FALCON-A processor and the programmer's view of its architecture.

📝 Lecture Summary

Instruction Set Architecture (ISA) Design: Outline of the thinking process

In this module, we learn to appreciate, understand, and apply the approach adopted in designing an instruction set architecture by designing an ISA for a new processor named FALCON-A. FALCON-A stands for First Architecture for Learning Computer Organization and Networks (version A). The term Organization is intended to include Architecture and Design in this acronym.

Elements of the ISA

Before designing the ISA for FALCON-A, we examine the three key components that define any instruction set architecture:

1. The operations the processor can execute
2. Data access mode for use as operands in the operations defined
3. Representation of the operations in memory

The operations the processor can execute

All processors need to support at least three categories (or functional groups) of instructions:

• Arithmetic, Logic, Shift
• Data Transfer
• Control

ISA Design Steps – Step 1

We need to think of all instructions of each type that ought to be supported. The following instructions will be included in the ISA for FALCON-A:

Arithmetic: add, addi (add immediate), subtract, subtract-immediate, multiply, divide

Logic: and, and-immediate, or, or-immediate, not

Shift: shift left, shift right, arithmetic shift right

Data Transfer: Data transfer between registers, moving constants to registers, load operands from memory to registers, store from registers to memory, and movement of data between registers and input/output devices

Control: Jump instructions with various conditions, call and return from subroutines, instructions for handling interrupts

Miscellaneous instructions: Instructions to clear all registers, the capability to stop the processor, ability to "do nothing", etc.

ISA Design Steps – Step 2

Once we have decided on the instructions, the second step is to select suitable mnemonics for these instructions. The following mnemonics have been selected:

Arithmetic: add, addi, sub, subi, mul, div

Logic: and, andi, or, ori, not

Shift: shiftl, shiftr, asr

Data Transfer: load, store, in, out, mov, movi

Control: jpl, jmi, jnz, jz, jump, call, ret, int, iret

Miscellaneous: nop, reset, halt

ISA Design Steps – Step 3

The next step is to decide upon the number of bits to be reserved for the op-code part of the instructions. Since we have 32 instructions in the instruction set, 5 bits will suffice (as 2⁵ = 32) to encode these op-codes.

ISA Design Steps – Step 4

The fourth step is to assign op-codes to these instructions. The assigned op-codes are shown below:

Arithmetic: add (0), addi (1), sub (2), subi (3), mul (4), div (5)

Logic: and (8), andi (9), or (10), ori (11), not (14)

Shift: shiftl (12), shiftr (13), asr (15)

Data Transfer: load (29), store (28), in (24), out (25), mov (6), movi (7)

Control: jpl (16), jmi (17), jnz (18), jz (19), jump (20), call (22), ret (23), int (26), iret (27)

Miscellaneous: nop (21), reset (30), halt (31)

These instructions with their op-codes are listed in binary form as they would appear in machine instructions of FALCON-A.

Data access mode for operations

The ISA defines, besides the instructions implemented, the resources each instruction can access: the number of registers available, the number of registers each instruction can access, which instructions are allowed to access memory, any special registers, constants, and alternatives to general-purpose registers.

ISA Design Steps – Step 5

We now need to select the number and types of operands for various instructions.

ALU instructions may have 2 to 3 registers as operands. In case of 2 operands, a constant (an immediate operand) may be included in the instruction.

For load/store type instructions, we require a register to hold the data to be loaded/stored, another register to hold the base address for memory access, and a field for specifying the constant that is the displacement to the base address.

In jump instructions, we require a field for specifying the register holding the value to be compared as the condition for the branch, as well as a destination address specified as a constant.

Once we have decided on the number and types of operands, we need to assign specific bit-fields in the instruction for each operand. The number of bits required to represent each operand will determine the instruction word size. For FALCON-A, we reserve eight general-purpose registers. To encode a register, 3 bits are required (as 2³ = 8).

The instructions for FALCON-A will have a general format with four different formats, depending on the actual number of operands in a particular instruction.

ISA Design Steps – Step 6

The next step is the design of memory and its organization. The number of memory cells depends on the size of the Program Counter (PC) register and the size of the address bus. This is because these sizes limit how many memory cells can be referred to for loading an instruction. Additionally, the size of the data bus limits the size of the memory word that can be referred to in a single clock cycle.

ISA Design Steps – Step 7

We need to specify which instructions will be allowed to access the memory. Since FALCON-A is intended to be a RISC-like machine, only the load/store instructions will be allowed to access memory.

🔑 Definition — RISC: Reduced Instruction Set Computer, a processor design philosophy that uses a small, highly optimized set of instructions.

ISA Design Steps – Step 8

Next we need to select the memory-addressing modes. The lecture lists the types of addressing modes supported for load/store instructions in FALCON-A.

FALCON-A: Introduction

FALCON stands for First Architecture for Learning Computer Organization and Networks. It is a 'RISC-like' general-purpose processor that will be used as a teaching aid for this course. Although FALCON-A is a simple machine, it is powerful enough to explain a variety of fundamental concepts in Computer Architecture.

Programmer's view of the FALCON-A

FALCON-A is an example of a GPR (General Purpose Register) computer. The programmer's view reveals the CPU contains a register file of 8 registers, named R0 through R7. Each register is 16 bits in length. Aside from these, there are two special-purpose registers: the Program Counter (PC) and the Instruction Register (IR).

🔑 Definition — Big-endian: A byte ordering format where the most significant byte (MSB) is stored at the smallest memory address.

The main memory is organized as 2¹⁶ x 8 bits, i.e., 2¹⁶ cells of 1 byte each. The memory word size is 2 bytes (or 16 bits). The input/output space is 256 bytes (8-bit I/O ports). Storage in registers and memory is in the big-endian format.

💡 Why this matters: Understanding the programmer's view gives you the complete picture of all resources available to the programmer, including register sizes, memory organization, and data representation, which are essential for writing and understanding programs.

⭐ Key Takeaways

The ISA design process for FALCON-A follows eight systematic steps from selecting operations to defining addressing modes. The FALCON-A supports 32 instructions across arithmetic, logic, shift, data transfer, control, and miscellaneous categories, all encoded using 5-bit op-codes. The processor has 8 general-purpose registers (16 bits each), two special-purpose registers (PC and IR), and memory organized as 2¹⁶ × 8 bits with 16-bit word size. As a RISC-like machine, only load/store instructions can access memory, and data is stored in big-endian format. The five addressing modes supported for load/store operations enable flexible memory access patterns using base registers and displacement values.

🧠 Quick Revision Questions

1. How many bits are required for the op-code field in FALCON-A, and why?
2. What are the three key components that define any instruction set architecture?
3. Which category of instructions is allowed to access memory in FALCON-A, and why?
4. How many general-purpose registers does FALCON-A have, and what is the size of each register?
5. What does the acronym FALCON stand for, and what type of processor architecture does it represent?

📘 Lecture 8 — ISA of the FALCON-A

📖 Overview: This lecture introduces the Instruction Set Architecture (ISA) of the FALCON-A processor, a simplified 16-bit processor used for learning computer architecture concepts. It covers the notation for registers and memory, instruction formats, and all the instructions grouped by type, providing the foundation for understanding how a processor executes programs.

🗂️ Topics Covered

The lecture begins with the notation used for registers and memory in the FALCON-A, including the big-endian format and concatenation for 16-bit words. It then details the processor's features, such as fixed-length 16-bit instructions and load/store architecture. The core of the lecture is a thorough walkthrough of all four instruction format types (I, II, III, IV) and the instructions that belong to each, including arithmetic, control, and data transfer operations. Finally, several examples are provided to demonstrate instruction identification, addressing modes, branch conditions, and binary encoding.

📝 Lecture Summary

Notation and Memory Organization for FALCON-A

The lecture begins by defining the notation for the FALCON-A. The contents of a register are referred to by enclosing the register name in square brackets (e.g., R[3] means the contents of register 3). Similarly, memory contents are referred to as M[8] for the contents of memory at location 8. Since the FALCON-A's memory is organized into 1-byte cells but its word size is 2 bytes, two adjacent memory cells make up a memory word. To refer to a 16-bit memory word, a concatenation notation is used, represented by the symbol ©. For example, the 16-bit memory word at location 8 is written as M[8]©M[9].

🔑 Definition — Big-endian: A byte ordering format where the largest numbered byte is placed at the most significant position in a word. The FALCON-A uses big-endian for bytes, but little endian (smallest numbered byte at the least-significant position) within each byte.

FALCON-A Features and Instruction Formats

The FALCON-A processor has fixed-length instructions, each 16 bits (2 bytes) long. It supports only load/store instructions for memory access, meaning arithmetic and logical operations are performed on registers. The three categories of instructions are arithmetic (including logical), control (for changing program flow), and data transfer (moving data between processor and memory). There are four instruction formats:

• Type I: Contains a 5-bit op-code (bits 11-15) and the rest of the bits are unused.
• Type II: Has a 5-bit op-code, a 3-bit register field (ra), and an 8-bit constant/immediate field (c2).
• Type III: Contains a 5-bit op-code, two 3-bit register fields (destination rd and source rs), and a 5-bit immediate operand field (c1).
• Type IV: Contains a 5-bit op-code, two 3-bit register fields (destination rd and source rs), and a 3-bit constant field (c1), plus two unused bits.

To encode the eight general-purpose registers (R0-R7) in binary, 3 bits are required. Register R0 has special usage; for example, in load/store operations, its value is considered zero. The binary encoding of registers is given in a table.

Type I Instructions

Five instructions belong to Type I, as they take no operands.

1. nop (op-code = 21): Instructs the processor to do no operation. Useful in pipelining.
2. reset (op-code = 30)
3. halt (op-code = 31)
4. int (op-code = 26)
5. iret (op-code = 27)

Type II Instructions

Nine instructions belong to Type II. They have a single register operand and an 8-bit jump/displacement or constant value.

1. movi (op-code = 7): Loads a register with a constant. 📌 Example: movi R3, 56 → R[3] ← 56
2. in (op-code = 24): Loads a register from an input device. 📌 Example: in R3, 57 → R[3] ← IO[57]
3. out (op-code = 25): Moves data from a register to an output device. 📌 Example: out R7, 34 → IO[34] ← R[7]
4. ret (op-code = 23): Returns control from a subroutine by setting PC to the value in a register. 📌 Example: ret R3 → PC ← R[3]
5. jz (op-code = 19): Conditional jump if the register value is zero. 📌 Example: jz r3, [4] → (R[3]=0): PC ← PC+4
6. jnz (op-code = 18): Conditional jump if the register value is not zero. 📌 Example: jnz r4, [variable] → (R[4]≠0): PC ← PC+variable
7. jpl (op-code = 16): Conditional jump if the register value is positive. 📌 Example: jpl r3, [label] → (R[3]≥0): PC ← PC+(label-PC)
8. jmi (op-code = 17): Conditional jump if the register value is negative. 📌 Example: jmi r7, [address] → (R[7]<0): PC ← PC+address
9. jump (op-code = 20): Unconditional jump. Allows direct, indirect, PC-relative (near), and register-relative (far) jumps. 🔑 Definition — PC-relative jump: When the ra field is zero, the PC is incremented by the sign-extended value of the c2 field. Formula: PC ← PC + (8©C2<7>) © C2<7..0> 🔑 Definition — Register-relative jump: When the ra field is non-zero, the PC is assigned the sum of the sign-extended constant and the value of the specified register. Formula: PC ← R[ra] + (8©C2<7>) © C2<7..0> 📌 Note: The compiler handles the interpretation of the c2 field as a constant, variable, label, or address. The machine code contains an 8-bit constant that is added to the PC at run-time.

Type III Instructions

Nine instructions belong to Type III. They have a destination register, a source register, and a 5-bit constant/immediate operand.

1. andi (op-code = 9): Bit-wise AND of a register and a constant. 📌 Example: andi r4, r3, 5 → R[4] ← R[3] & 5
2. addi (op-code = 1): Add a constant to a register. 📌 Example: addi r4, r3, 4 → R[4] ← R[3] + 4
3. subi (op-code = 3): Subtract a constant from a register. 📌 Example: subi r5, r7, 9 → R[5] ← R[7] - 9
4. ori (op-code = 11): Bit-wise OR of a register and a constant. 📌 Example: ori r4, r7, 3 → R[4] ← R[7] ~ 3
5. shiftl (op-code = 12): Shift the bits of a register to the left by a constant. 📌 Example: shiftl r4, r3, 7
6. shiftr (op-code = 13): Shift the bits of a register to the right by a constant. 📌 Example: shiftr r4, r3, 9
7. asr (op-code = 15): Arithmetic shift right, which divides a signed binary number by 2 for each shift. The sign-bit is left unchanged. 📌 Example: asr r1, r2, 5 This divides the value in r2 by 10 and places the result in r1.
8. load (op-code = 29): Load a register from a memory location. The address is the sum of a register and a constant. 📌 Example: load r1, [r4 + 15] → R[1] ← M[R[4] + 15]
9. store (op-code = 28): Store a register value to a memory location. The address is the sum of a register and a constant. 📌 Example: store r6, [r7 + 13] → M[R[7] + 13] ← R[6]

Type III Modified Instructions

Three instructions use a modified form of Type III, where the c1 field is unused.

1. mov (op-code = 6): Copy data from one register to another. 📌 Example: mov r4, r3 → R[4] ← R[3]
2. not (op-code = 14): Invert the bits of a register. 📌 Example: not r4, r2 → R[4] ← !R[2]
3. call (op-code = 22): Procedure call. Saves the return address (current PC) in one register and then loads a new address into the PC from another register. 📌 Example: call r4, r3 → R[4] ← PC, PC ← R[3]

Type IV Instructions

Six instructions belong to Type IV, which operates on three registers: a destination and two sources.

1. add (op-code = 0): Add two registers. 📌 Example: add r4, r3, r5 → R[4] ← R[3] + R[5]
2. sub (op-code = 2): Subtract one register from another. 📌 Example: sub r4, r3, r5 → R[4] ← R[3] - R[5]
3. mul (op-code = 4): Multiply two registers. The result uses a concatenation of R0 and the destination register. 📌 Example: mul r5, r7, r1 → R[0] © R[5] ← R[7] * R[1]
4. div (op-code = 5): Divide one register by another. The result and remainder are stored. 📌 Example: div r4, r7, r2 → R[4] ← R[0]©R[7]/R[2], R[0] ← R[0]©R[7]%R[2]
5. and (op-code = 8): Bit-wise AND of two registers. 📌 Example: and r1, r4, r5 → R[1] ← R[4] & R[5]
6. or (op-code = 10): Bit-wise OR of two registers. 📌 Example: or r6, r7, r2 → R[6] ← R[7] ~ R[2]

Examples for FALCON-A

This section provides four examples to solidify the concepts:

1. Identification of instruction types and operands: Given a list of instructions, the task is to identify their format type (I, II, III, or IV) and the values of their fields (op-code, ra, rb, rc, c1, c2).
2. Addressing modes and RTL description: For instructions like load and store, the addressing mode is register-relative. The RTL description explains the operation's meaning.
3. Branch condition and status of the PC: For branch instructions like jz, jnz, jpl, and jmi, the condition for the branch (e.g., "if zero") and the new PC value after a true branch must be determined.
4. Binary encoding of instructions: Given instructions, the binary encoding of each field (op-code, register numbers, constants) is extracted using the instruction format definitions, op-code tables, and register encoding table.

💡 Why this matters: Understanding how to encode an instruction into its binary format is the fundamental step in designing an assembler or understanding machine code.

⭐ Key Takeaways

The FALCON-A is a 16-bit load/store architecture with fixed-length 16-bit instructions, divided into four formats (I, II, III, IV) that dictate the number and type of operands. The lecture details all 27 instructions, including their op-codes, operands, and RTL definitions. Students must memorize the instruction formats and the field widths, the special role of R0, and how conditional jumps and the subroutine call/return mechanism work. Finally, the ability to identify an instruction's format, its binary encoding, and its RTL meaning is essential for exam problems.

🧠 Quick Revision Questions

1. What are the three categories of instructions supported by the FALCON-A, and what is the purpose of each?
2. How many bits are in a FALCON-A instruction? How many bits are used for the op-code?
3. Describe the difference between a Type III and a Type III Modified instruction.
4. Write the RTL for the jump instruction when ra is non-zero (register-relative jump).
5. What is the binary encoding for the instruction add r4, r3, r5? (Use the op-code and register encoding tables).

📘 Lecture 9 — Description of FALCON-A and EAGLE using RTL

📖 Overview: This lecture explores how Register Transfer Language (RTL) is used to formally describe both the static and dynamic behavior of the FALCON-A processor. It then introduces the EAGLE processor, an accumulator-based machine, and discusses its limitations, followed by the design improvements in the Modified EAGLE. Understanding RTL is crucial for specifying processor functionality before hardware implementation.

🗂️ Topics Covered

This lecture covers the use of Behavioral and Structural RTL to describe the FALCON-A processor, including register specification, field naming, processor state, and dynamic instruction execution. It then presents the EAGLE processor's architecture, instruction formats, and complete instruction set, followed by an analysis of its limitations and the enhancements introduced in the Modified EAGLE, including a dedicated accumulator and flag register.

📝 Lecture Summary

Use of Behavioral Register Transfer Language (RTL) to describe the FALCON-A

The use of RTL (an acronym for the Register Transfer Language) to describe the FALCON-A is discussed in this section. FALCON-A is the sample machine we are building in order to enhance our understanding of processors and their architecture.

Behavior vs. Structure

Computer design involves various levels of abstraction. The behavioral description of a machine is a higher level of abstraction, as compared with the structural description. A top-down approach is adopted in computer design. Designing a computer typically starts with defining the behavior of the overall system. This is then broken down into the behavior of the different modules. The process continues, till we are able to define, design and implement the structure of the individual modules.

As mentioned earlier, we are interested in the behavioral description of our machine, the FALCON-A, in this section.

Register Transfer Language

The RTL is a formal way of expressing the behavior and structure of a computer.

Behavioral RTL is used to describe what a machine does, i.e. it is used to define the functionality the machine provides. Basically, the behavioral architecture describes the algorithms used in a machine, written as a set of process statements. These statements may be sequential statements or concurrent statements, including signal assignment statements and wait statements.

Structural RTL is used to describe the hardware implementation of the machine. The structural architecture of a machine is the logic circuit implementation (components and their interconnections), that facilitates a certain behavior (and hence functionality) for that machine.

Using RTL to describe the static properties of the FALCON-A

We can employ the RTL for the description of various properties of the FALCON-A that we have already discussed.

Specifying Registers: In RTL, we will refer to a register by its abbreviated, alphanumeric name, followed by the number of bits in the register enclosed in angle brackets < >. For instance, the instruction register (IR), of 16 bits (numbered 0 to 15), will be referred to as, IR<15..0>

Naming of the Fields in a Register: We can name the different fields of a register using the := notation. For example, to name the most significant bits of the instruction register as the operation code (or simply op), we may write:

op<4..0> := IR<15..11>

Note that using this notation to name registers or register fields will not create a new copy of the data or the register fields; it is simply an alias for an already existing register, or part of a register.

Fields in the FALCON-A Instructions: We now use the RTL naming operator to name the various fields of the RTL instructions. Naming the fields appropriately helps us make the study of the behavior of a processor more readable.

op<4..0>:= IR<15..11>: operation code field ra<2..0> := IR<10..8>: target register field rb<2..0> := IR<7..5>: operand or address index rc<2..0> := IR<4..2>: second operand c1<4..0> := IR<4..0>: short displacement field c2<7..0> := IR<7..0>: long displacement or the immediate field

We are already familiar with these fields, and their usage in the various instruction formats of the RTL.

Describing the Processor State using RTL: The processor state defines the contents of all the register internal to the CPU at a given time. Maintaining or restoring the machine or processor state is important to many operations, especially procedure calls and interrupts; the processor state needs to be restored after a procedure call or an interrupt so normal operation can continue. Our processor state consists of the following:

• PC<15..0>: program counter (the PC holds the memory address of the next instruction)
• IR<15..0>: instruction register (used to hold the current instruction)
• Run: one bit run/halt indicator
• Strt: start signal
• R[0..7]<15..0>: 8 general purpose registers, each consisting of 16 bits

FALCON-A in a black box: The given figure shows what a processor appears as to a user. We see a start button that is basically used to start up the processor, and a run indicator that turns on when the processor is in the running state. There may be several other indicators as well. The start button as well as the run indicator can be observed on many machines.

Using RTL to describe the dynamic properties of the FALCON-A

We have just described some of the static properties of the FALCON-A. The RTL can also be employed to describe the dynamic behavior of the processor in terms of instruction interpretation and execution.

Conditional expressions can be specified using the RTL. For instance, we may specify a conditional subtraction operation employing RTL as:

(op=2) : R[ra] ← R[rb] - R[rc];

This instruction means that "if" the operation code of the instruction equals 2 (00010 in binary), then subtract the value stored in register rc from that of register rb, and store the resulting value in register ra.

Effective address calculations in RTL (performed at runtime): The operand or the destination address may not be specified directly in an instruction, and it may be required to compute the effective address at run-time. Displacement and relative addressing modes are instances of such situations. RTL can be used to describe these effective address calculations.

• Displacement address: A displacement address is calculated, as shown: disp<15..0> := (R[rb]+ (11α c1<4>)© c1<4..0>); This means that the address is being calculated by adding the constant value specified by the field c1 (which is first sign extended), to the value specified by the register rb.

• Relative address: A relative address is calculated by adding the displacement to the contents of the program counter register. The constant is first sign-extended. In RTL this is represented as: rel<15..0>:=PC+(8αc2<7>)©c2<7..0>;

Range of memory addresses: Using the displacement or the relative addressing modes, there is a specific range of memory addresses that can be accessed.

• Range of addresses when using direct addressing mode (displacement with rb=0):

  • If c1<4>=0 (positive displacement) absolute addresses range: 00000b to 01111b (0 to +15)
  • If c1<4>=1 (negative displacement) absolute addresses range: 11111b to 10000b (-1 to -16)

• Address range in case of relative addressing:

  • The largest positive value that can be specified using 8 bits (since we have only 8 bits available in c2<7..0>), is 2⁷-1, and the most negative value that can be represented using the same is 2⁷. Therefore, the range of addresses or locations that can be referred to using this addressing mode is 127 locations forward or 128 locations backward from the Program Counter (PC).

Instruction Fetch Operation (using RTL)

We will now employ the notation that we have learnt to understand the fetch-execute cycle of the FALCON-A processor.

The RTL notation for the instruction fetch process is:

instruction_Fetch := (
!Run&Strt : Run ← 1,
Run : (IR ← M[PC], PC ← PC + 2;
instruction_Execution) );

This is how the instruction-fetch phase of the fetch-execute cycle for FALCON-A can be represented using RTL. Recall that := is the naming operator, ! implies a logical NOT, & implies a logical AND, ← represents a transfer operation, ; is used to separate sequential statements, and concurrent statements are separated by ,. We can observe that in the instruction_Fetch phase, if the machine is not in the running state and the start bit has been set, then the run bit is also set to true. Concurrently, an instruction is fetched from the instruction memory; the program counter (PC) holds the next instruction address, so it is used to refer to the memory location from where the instruction is to be fetched. Simultaneously, the PC is incremented by 2 so it will point to the next instruction. (Recall that our instruction word is 2 bytes long, and the instruction memory is organized into 1-byte cells). The next step is the instruction execution phase.

Difference between , and ; in RTL: We again highlight the difference between the , and ;. Statements separated by a , take place during the same clock pulse. In other words, the order of execution of statements separated by , does not matter.

On the other hand, statements separated by a ; take place on successive clock pulses. In other words, if statements are separated by ; the one on the left must complete before the one on the right starts. However, some things written with one RTL statement can take several clocks to complete.

We return to our discussion of the instruction-fetch phase. The statement !Run&Strt : Run ← 1 is executed when 'Run' is 0, and 'Strt' is 1, that is, Strt has been set. It is used to set the Run bit. No action takes place when both 'Run' and 'Strt' are 0. The following two concurrent register transfers are performed when 'Run' is set to 1, (as : is a conditional operator; if the condition is met, the specified action is taken).

IR ← M[PC] PC ← PC + 2

Since these instructions appear concurrent, and one of the instructions is using the value of PC that the other instruction is updating, a question arises; which of the two values of the PC is used in the memory access? As a rule, all right hand sides of the register transfers are evaluated before the left hand side is evaluated/updated. In case of simultaneous register transfers (separated by a ,), all the right hand side expressions are evaluated in the same clock-cycle, before they are assigned. Therefore, the old, un-incremented value of the PC is used in the memory access, and the incremented value is assigned to the PC afterwards. This corresponds to "master-slave" flip-flop operation in logic circuits.

This makes the PC point to the next instruction in the instruction memory. Once the instruction has been fetched, the instruction execution starts. We can also use i.F for instruction_Fetch and i.E for instruction_Execution. This will make the Fetch operation easy to write.

iF := ( !Run&Strt : Run ← 1, Run : (IR ← M[PC], PC ← PC + 2; iE ) );

Instruction Execution (Describing the Execute operation using RTL)

Once an instruction has been fetched from the instruction memory, and the program counter has been incremented to point to the next instruction in the memory, instruction execution commences. In the instruction fetch-execute cycle we showed in the preceding discussion, the entire instruction execution code was aliased iE (or instruction_Execution), through the assignment operator :=. Now we look at the instruction execution in detail.

iE := (
(op<4..0>= 1) : R[ra] ← R[rb]+ (11α c1<4>)© c1<4..0>,
(op<4..0>= 2) : R[ra] ← R[rb]-R[rc],
. . .
. . .
(op<4..0>=31) : Run ← 0,); iF );

As we can see, the instruction execution can be described in RTL by using a long list of concurrent, conditional operators that are inherently 'disjoint'. Being inherently disjointed implies that at any instance, only one of the conditions can be met; hence one of the statements is executed. The long list of statements is basically all of the instructions that are a part of the FALCON-A instruction set, and the condition for their execution is related to the operation code of the instruction fetched. We will take a closer look at the entire list in our subsequent discussion. Notice that in the instruction execute phase, besides the long list of concurrent, disjoint instructions, there is also the instruction fetch or iF sequenced at the end. This implies that once one of the instructions from the list is executed, the instruction fetch is called to fetch the next instruction. As shown before, the instruction fetch will call the instruction execute after fetching a certain instruction, hence the instruction fetch-execute cycle continues.

Jump instructions: Some of the instructions listed for the instruction execution phase are jump instruction, as shown.

• If op-code is 20, the branch is taken unconditionally (the jump instruction). (op<4..0>=20) : (cond : (PC ← R[ra]+C2(sign extended)),
• If the op-code is 16, the condition for branching is checked, and if the condition is being met, the branch is taken; otherwise it remains untaken, and normal program flow will continue. (op<4..0>= 16) : (cond : (PC ← PC+C2 (sign extended))

Arithmetic and Logical Instructions: Several instructions provide arithmetic and logical operations functionality.

• If op-code is 0, the instruction is 'add'. The values in register rb and rc are added and the result is stored in register ra. (op<4..0>=0) : R[ra] ← R[rb] + R[rc],
• If op-code is 1, the instruction is addi; the immediate constant specified by the constant field C1 is sign extended and added to the value in register rb. The result is stored in the register ra. (op<4..0>=1) : R[ra] ←R[rb] + (11α C1<4>)© C1<4..0>,
• For op-code 2, value stored in register rc is subtracted from the value stored in register rb, and the result is stored in register ra. (op<4..0>=2) : R[ra] ← R[rb] - R[rc],
• If op-code is 3, the immediate constant C1 is sign-extended, and subtracted from the value stored in rb. Result is stored in ra. (op<4..0>=3) : R[ra] ← R[rb]- (11α C1<4>)© C1<4..0>,
• For op-code 4, values of rb and rc register are multiplied and result is stored in the destination register. (op<4..0>=4) : R[ra] ← R[rb] * R[rc],
• If the op-code is 5, contents of register rb are divided by the value stored in rc, result is concatenated with 0s, and stored in ra. The remainder is stored in R0. (op<4..0>=5) : R[ra] ← R[0] ©R[rb]/R[rc], R[0] ← R[0] ©R[rb]%R[rc],
• If op-code equals 8, bit-wise logical AND of rb and rc register contents is assigned to ra. (op<4..0>=8) : R[ra] ← R[rb] & R[rc],
• If op-code equals 10, bit-wise logical OR of rb and rc register contents is assigned to ra. (op<4..0>=10) : R[ra] ← R[rb] ~ R[c],
• For op-code 14, the contents of register specified by field rc are inverted (logical NOT is taken), and the resulting value is stored in register ra. (op<4..0>=14) : R[ra] ← ! R[rc],

Shift Instructions: The shift instructions are also a part of the instruction set for FALCON-A.

• If the op-code is 12, the contents of the register rb are shifted right N bits. N is the number specified in the constant field. The space that has been created due to the shift out of bits is filled with 0s through concatenation. (op<4..0>=12) : R[ra]<15..0> ← R [rb]<(15-N)..0>©(Nα0),
• If op-code is 13, rb value is shifted left, and 0s are inserted in place of shifted out contents at the right side of the value. The result is stored in ra. (op<4..0>=13) : R[ra]<15..0> ← (Nα0)©R [rb]<(15)..N>,
• For op-code 15, arithmetic shift right operation is carried out on the value stored in rb. The arithmetic shift right shifts a signed binary number stored in the source register to the right, while leaving the sign-bit unchanged. Note that α means replication, and © means concatenation. (op<4..0>=15) : R[ra]<15..0> ← Nα(R [rb]<15>)© (R [rb]<15..N>),

Data transfer instructions: Several of the instructions belong to the data transfer category.

• Op-code 29 specifies the load instruction, i.e. a memory location is referenced and the value stored in the memory location is copied to the destination register. The effective address of the memory location to be referenced is calculated by sign extending the immediate field, and adding it to the value specified by register rb. (op<4..0>=29) : R[ra]← M[R[rb]+ (11α C1<4>)© C1<4..0>],
• A value is stored back to memory from a register using the op-code 28. The effective address in memory where the value is to be stored is calculated in a similar fashion as the load instruction. (op<4..0>=28) : M[R[rb]+ (11α C1<4>)© C1<4..0>] ← R [ra],
• The move instruction has the op-code 6. The contents of one register are copied to another register through this instruction. (op<4..0>=6) : R[ra] ← R[rb],
• To store an immediate value (specified by the field C2 of the instruction) in a register, the op-code 7 is employed. The constant is first sign-extended. (op<4..0>=7) : R[ra] ← (8αC2<7>)©C2<7..0>,
• If the op-code is 24, an input is obtained from a certain input device, and the input word is stored into register ra. The input device is selected by specifying its address through the constant C2. (op<4..0>=24) : R[ra] ← IO[C2],
• If the op-code is 25, an output (the register ra value) is sent to an output device (where the address of the output device is specified by the constant C2). (op<4..0>=25) : IO[C2] ← R[ra],

Miscellaneous instructions: Some more instructions included in the FALCON-A are:

• The no-operation (nop) instruction, if the op-code is 21. This instructs the processor to do nothing. (op<4..0>= 21) : ,
• If the op-code is 31, setting the run bit to 0 halts the processor. (op<4..0>= 31) : Run ← 0, Halt the processor (halt)

At the end of this concurrent list of instructions, there is an instruction i.F (the instruction fetch). Hence when an instruction is executed, the next instruction is fetched, and the cycle continues, unless the processor is halted.

); iF );

The EAGLE (Original version)

Another processor that we are going to study is the EAGLE. We have developed two versions of it, an original version, and a modified version that takes care of the limitations in the original version. The study of multiple processors is going to help us get thoroughly familiar with the processor design, and the various possible designs for the processor. However, note that these machines are simplified versions of what a real machine might look like.

Introduction

The EAGLE is an accumulator-based machine. It is a simple processor that will help us in our understanding of the processor design process. EAGLE is characterized by the following:

• Eight General Purpose Registers of the CPU. These are named R0, R1...R7. Each register is 16-bits in length.
• Two 16-bit system registers transparent to the programmer are the Program Counter (PC) and the Instruction Register (IR). (Being transparent to the programmer implies the programmer may not directly manipulate the values to these registers. Their usage is the same as in any other processor)
• Memory word size is 16 bits
• The available memory space size is 2¹⁶ bytes
• Memory organization is 2¹⁶ x 8 bits. This means that there are 2¹⁶ memory cells, each one byte long.
• Memory is accessed in 16 bit words (i.e., 2 byte chunks)
• Little-endian byte storage is employed.

EAGLE: Notation

Let us take a look at the notation that will be employed for the study of the EAGLE.

Enclosing the register name in square brackets refers to register contents; for instance, R[3] means contents of register R3.

Enclosing the location address in square brackets, preceded by 'M', lets us refer to memory contents. Hence M[8] means contents of memory location 8.

As little endian storage is employed, a memory word at address x is defined as the 16 bits at address x+1 and x. For instance, the bits at memory location 9,8 define the memory word at location 8. So employing the special notation for 16-bit memory words, we have:

M [8]<15...0>:=M [9]©M [8]

Where © is used to represent concatenation.

EAGLE Features

The following features characterize the EAGLE.

• Instruction length is variable. Instructions are either 8 bits or 16 long, i.e., instruction size is either 8-bits or 16-bits.
• The instructions may have either one or two operands.
• The only way to access memory is through load and store instructions.
• Limited addressing modes are supported.

EAGLE: Instruction Formats

There are five instruction formats for the EAGLE. These are:

• Type Z Instruction Format: The Z format instructions are half-word (1 byte) instructions, containing just the op-code field of 8 bits.
• Type Y Instruction Format: The type Y instructions are also half-word. There is an op-code field of 5 bits, and a register operand field ra.
• Type X Instruction Format: Type X instructions are also half-word instructions, with a 2-bit op-code field, and two 3-bit operand register fields.
• Type W instruction format: The instructions in this type are 1-word (16-bit) in length. 8 bits are reserved for the op-code, while the remaining 8 bits form the constant (immediate value) field.
• Type V instruction format: Type V instructions are also 1-word instructions, containing an op-code field of 5 bits, an operand register field of 3 bits, and 8 bits for specifying a constant.

Encoding of the General Purpose Registers

The encoding for the eight GPRs is shown in the table. These binary codes are to be used in place of the 'place-holders' ra, rb in the actual instructions of the processor EAGLE.

Listing of EAGLE instructions with respect to instruction formats

Type Z: There are four type Z instructions:

• halt (op-code=250): This instruction halts the processor.
• nop (op-code=249): nop, or the no-operation instruction stalls the processor for the time of execution of a single instruction. It is useful in pipelining.
• init (op-code=251): This instruction is used to initialize all the registers, by setting them to 0.
• reset (op-code=248): This instruction is used to initialize the processor to a known state. In this instruction the control step counter is set to zero so that the operation begins at the start of the instruction fetch and besides this PC is also set to a known value so that machine operation begins at a known instruction.

Type Y: Seven instructions of the processor are of type Y. These are:

• add (op-code=11): The type Y add instruction adds register ra's contents to register R0. For example, add r1. In the behavioral RTL, we show this as R[0] ← R[1]+R[0].
• and (op-code=19): This instruction obtains the logical AND of the value stored in register specified by field ra and the register R0, and assigns the result to R0, as shown in the example: and r5 which is represented in RTL as R[0] ← R[1]&R[0].
• div (op-code=16): This instruction divides the contents of register R0 by the value stored in the register ra, and assigns result to R0. The remainder is stored in the divisor register, as shown in example: div r6. In RTL, this is R[0] ← R[0]/R[6], R[6] ← R[0]%R[6].
• mul (op-code=15): This instruction multiplies the values stored in register R0 and the operand register, and assigns the result to R0. For example: mul r4. In RTL, we specify this as R[0] ← R[0]*R[4].
• not (op-code=23): The not instruction inverts the operand register's value and assigns it back to the same register, as shown in the example: not r6, R[6] ← ! R[6].
• or (op-code=21): The or instruction obtains the bit-wise OR of the operand register's and R0's value, and assigns it back to R0. An example: or r5, R[0] ← R[0] ~ R[5].
• **sub

📘 Lecture 10 — The FALCON-E and ISA Comparison

📖 Overview: This lecture introduces the FALCON-E processor, a simple yet instructive general-purpose register machine designed for learning computer organization. It then provides a comprehensive comparison of the instruction set architectures (ISAs) of the EAGLE, FALCON-A, FALCON-E, and SRC processors, examining key design parameters that affect performance and code density.

🗂️ Topics Covered

The lecture begins with the introduction of the FALCON-E processor, covering its programmer’s view (registers and memory), notation, features, instruction formats (types A, B, C, D), and the complete instruction set including data transfer and ALU instructions. The second half presents a detailed comparison of ISAs across the EAGLE, FALCON-A, FALCON-E, and SRC processors, analyzing instruction length, number of operands, register files, memory specifications, addressing modes, control flow instructions, and common/unique instructions, concluding with a code density problem.

📝 Lecture Summary

The FALCON-E

Introduction

FALCON stands for First Architecture for Learning Computer Organization and Networks. The FALCON-E is a General-Purpose Register machine characterized by eight 32-bit General Purpose Registers (GPRs: R0-R7), two special registers (BP and SP), the Program Counter (PC) and Instruction Register (IR). Memory is organized as 2³² bytes of 1-byte cells, accessed in 32-bit words using little-endian byte storage.

🔑 Definition — Little Endian: The least significant byte is stored first (at the lowest memory address). 📐 Format: M[8]<31…0> := M[11]©M[10]©M[9]©M[8] → The memory word at address 8 is formed by concatenating bytes at addresses 11, 10, 9, and 8. 💡 Why this matters: Understanding endianness is critical for data interpretation across different systems.

FALCON-E Features: Fixed 32-bit instruction size (1 word), all ALU instructions have three operands, and memory access is only through load and store instructions with limited addressing modes.

FALCON-E Instruction Formats: Four formats are supported.

• Type A: 5-bit op-code, remaining bits unused or specify a displacement. Used for nop, ret, iret, near jmp.
• Type B: 5-bit op-code, a register operand (ra), and an immediate/displacement field. Used for push, pop, ld, st.
• Type C: 5-bit op-code, two 3-bit operand registers (rb=source, ra=destination), a 17-bit immediate/displacement, and a 3-bit function field. Used for lds, sts, in, out, addi, andi, ori.
• Type D: 5-bit op-code, three 3-bit operand registers (ra, rb, rc), 14 unused bits, and a 3-bit function field. Used for add, sub, and, or.

Encoding for GPRs: Each register field is 3 bits (2³ = 8 registers). R0=000, R1=001, R2=010, R3=011, R4=100, R5=101, R6=110, R7=111. SP and BP are encoded separately for use in load/store instructions (SP=010, BP=011).

Instructions, Instruction Formats: Detailed review of instructions by format.

• Type A Instructions: nop (op-code 0, do nothing), ret (op-code 15, return from procedure/interrupt), iret (op-code 17, return to specified address), near jmp (op-code 18, PC-relative jump).
• Type B Instructions: push (op-code 8, push register onto stack), pop (op-code 9, pop stack into register), ld (op-code 10, load from immediate address), st (op-code 12, store to immediate address).
• Type C Instructions: Data transfer: lds (op-code 4, load with displacement), sts (op-code 5, store with displacement), in (op-code 6, load from I/O device with displacement), out (op-code 7, store to I/O device with displacement). ALU: addi (op-code 2, add immediate), andi (op-code 2, AND immediate), ori (op-code 2, OR immediate).
  📌 Example (lds): lds R3, R4(56) → R[3] ← M[R[4] + 56]
  📌 Example (addi): addi R3, R4, 56 → R[3] ← R[4] + 56
• Type D Instructions: add (op-code 1, add registers), sub (op-code 1, subtract registers), and (op-code 1, AND registers), or (op-code 1, OR registers).
  📌 Example (add): add R3, R5, R6 → R[3] ← R[5] + R[6]

Falcon-E Instruction Summary: Tables group instructions by functionality (e.g., data transfer, ALU, control). These tables are provided in the lecture text.

Instruction Set Architecture Comparison

Classifying Instruction Set Architectures: Design choices for ISA critically affect code density (instructions to complete a task), cycles per instruction (CPI), and cycle time. Classification is based on instruction length, number/types of operands, register file, memory specs, data transfer instructions, control flow, and addressing modes.

Instruction Length: Fixed vs. variable. Fixed lengths (used by all RISC machines) simplify design but can waste space. Required length depends on instruction count, register file size, operand count, immediate field size, and desired code density.

• EAGLE: 2 bytes
• FALCON-A: 8 bytes
• FALCON-E: 4 bytes
• SRC: 4 bytes

Instruction types and sub-types: A table summarizes the number of instruction types and sub-types for each processor.

Number of operands in the instructions: Affects instruction length and code density. FALCON-A, FALCON-E, and SRC can have 3, 2, 1, or 0 operands. EAGLE has a maximum of 2 operands. Implicit operands (like an accumulator) reduce instruction size.

Number and Size of General Purpose Registers: More registers decrease memory traffic (accessing memory is slower). However, a very large register file requires more bits for encoding. Tables provide the number and size of registers for each processor.

Memory specifications: Includes memory space, organization, word size, and storage format. A table lists these specifications for the processors compared.

Data transfer instructions: Instructions for moving data between registers and memory.

• Register to register: EAGLE has limited transfers (accumulator only). FALCON-A has mov. FALCON-E has lds and sts. SRC has no direct instruction; can use addi with zero or store/load via memory.
• Register to memory: EAGLE supports load/store to accumulator only. FALCON-A, FALCON-E, and SRC support general load/store.
• Memory to memory: Not supported in any of the discussed processors.

Control Flow Instructions: Include branches (conditional), jumps (unconditional), calls, and returns.

• Conditional Branches: Conditions can be specified via condition codes (flags in ALU, used by EAGLE), a condition register, or compare and branch (used by all processors discussed). Compare and branch makes comparison part of the instruction.
• Size of jumps: All processors except SRC support PC-relative jumps. The displacement size (in bits) determines jump magnitude. A table specifies displacement sizes (e.g., EAGLE: 8 bits, FALCON-A: 26 bits).

Addressing Modes: Methods to specify operand addresses. Common modes: Immediate (constant in instruction), Register (value in register), Direct (constant is memory address), Register Indirect (register holds memory address), Displacement (register + constant), Relative (PC + constant), Indexed/Scaled (register + register, possibly with scaling), Auto increment/decrement (register value used then incremented/decremented). Complex modes reduce instruction count but increase implementation complexity. A table lists supported modes for each processor.

Displacement addressing mode: The most common mode. Displacement size affects efficient address calculation. A table specifies displacement field sizes (e.g., EAGLE: 8 bits, FALCON-E: 17 bits).

Instructions common to all Instruction Set Architectures: Arithmetic (add, addi, sub), Logical (and, andi, or, ori, not), Shift (right, left, arithmetic right), Data Movement (load, store), Control (conditional/unconditional branches, nop, reset). Assembly codes are listed in tables.

Instructions unique to each processor:

• EAGLE: movia (move immediate to accumulator), a2r (accumulator to register), r2a (register to accumulator), cla (clear accumulator).
• FALCON-A: ret (return from procedure, restoring PC from register ra: PC ← R[ra]).
• FALCON-E: push, pop, ldr (load with displacement), str (store with displacement), bl (branch if less), bg (branch if greater), muli, divi, xor, xori, ror, rori.
• SRC: ldr (load with PC-relative), lar (load with relative address), str (store with relative address), brlnv (never branch, save PC to register), brlpl (branch if positive, save return address), brlmi (branch if negative), brlzr (branch if zero), brlnz (branch if not zero).

Problem Comparison: Implements a = (b - 2) + 4c in all processors. EAGLE requires the most instructions (due to simpler ISA) while other processors achieve higher code density with fewer instructions.

⭐ Key Takeaways

You must understand that FALCON-E is a simple, RISC-like processor with a fixed 32-bit instruction size, 8 general-purpose registers, and a load-store architecture where memory is accessed only through explicit load and store instructions. The four instruction formats (A, B, C, D) differ in the number of operands and the presence of a function field, and you must be able to decode RTL for instructions like addi, lds, and add. For ISA comparison, you should know that instruction length, number of operands, register file size, and addressing modes all trade off between code density, design simplicity, and performance. Finally, be prepared to compare ISAs across the four processors, identifying unique instructions and how a common operation might be implemented differently, as demonstrated in the problem comparison.

🧠 Quick Revision Questions

1. What is the difference between Type A and Type D instructions in the FALCON-E?
2. How is the effective address calculated for a lds R3, R4(56) instruction? Write its RTL.
3. Which processors among EAGLE, FALCON-A, FALCON-E, and SRC use a fixed instruction length? What are their respective instruction sizes?
4. Explain the difference between condition code-based branching and compare-and-branch addressing modes. Which processors use which?
5. How can you perform a register-to-register copy in the SRC processor without a dedicated move instruction? Provide an example.

📘 Lecture 11 — CISC and RISC

📖 Overview: This lecture explores two fundamental microprocessor architectures: CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer). It examines a key CISC example—the Motorola MC68000—and a key RISC example—the SPARC architecture—to highlight their design philosophies, trade-offs, and impact on performance and programming.

🗂️ Topics Covered

The lecture begins with an examination of the Motorola MC68000, a classic CISC microprocessor with a complex instruction set, variable instruction lengths, and multiple addressing modes. It then introduces the SPARC architecture, a canonical RISC design emphasizing simple, fixed-length instructions, register windows, and a load/store model. The comparison illustrates the historical and technical motivations behind each approach, including considerations of code density, compiler complexity, and execution speed.

📝 Lecture Summary

A CISC microprocessor: The Motorola MC68000

This section details the Motorola MC68000, a CISC (Complex Instruction Set Computer) microprocessor. The MC68000 has a rich instruction set with many specialized instructions, variable-length instructions (from 2 to 10 bytes), and multiple addressing modes. It features 16 general-purpose data registers (D0–D7) and 8 address registers (A0–A7). The architecture supports powerful operations like memory-to-memory moves and complex instructions that perform multiple operations (e.g., a single instruction can fetch, operate on, and store data). The design prioritizes code density—using fewer instructions per task—at the cost of hardware complexity and variable execution times.

🔑 Definition — CISC: A computer architecture where individual instructions can execute multiple low-level operations (like memory access and arithmetic) in one line of code, often using variable instruction lengths and many addressing modes. 📐 Formula: Instruction length = from 2 to 10 bytes (variable) → meant complex decoding but compact code. 📌 Example: The MC68000 instruction MOVE.L (A0)+, D0 moves a 32-bit value from the memory address pointed to by address register A0 (post-incrementing A0) into data register D0. This single instruction accomplishes memory read, register increment, and data transfer—three operations—in one step, showing CISC’s power at the cost of execution complexity.

A RISC Architecture: The SPARC

This section introduces the SPARC (Scalable Processor Architecture), a classic RISC (Reduced Instruction Set Computer) design. RISC architectures emphasize a small, highly optimized set of instructions, each typically one word in size (32 bits fixed length). The SPARC uses a load/store architecture: only load and store instructions access memory; all other operations work on registers. A key feature is register windows, which provide a large number of overlapping register sets (usually 32 registers visible at a time out of a larger pool) to reduce memory traffic during function calls. Instructions are executed in a single cycle, simplifying the control logic and enabling pipelining. RISC designs prioritize simplicity and speed over code density.

🔑 Definition — RISC: A computer architecture where each instruction performs only one operation (e.g., add, load, store), using fixed-length instructions, a load/store model, and many registers to simplify hardware and enhance pipelining. 📐 Formula: Instruction length = 32 bits (fixed) → enables fast decoding and pipelining. 📌 Example: In SPARC, adding two numbers requires two separate instructions: LD [addr], %r1 (load data from memory address into register 1) and ADD %r1, %r2, %r3 (add register 1 and register 2, store result in register 3). This contrasts with CISC, where a single instruction might do all of this, showing RISC’s trade-off of more instructions per task for simpler, faster execution.

💡 Why this matters: Understanding CISC vs. RISC helps explain design choices in modern processors (like Intel’s x86 being CISC inside but often translating to RISC-like micro-ops) and performance optimization.

⭐ Key Takeaways

For the exam, remember that CISC (exemplified by MC68000) uses variable-length instructions, many addressing modes, and powerful single instructions that can perform multiple operations (e.g., memory fetch, add, store) to achieve high code density but with complex hardware and variable cycles per instruction. In contrast, RISC (exemplified by SPARC) uses fixed-length instructions, a load/store model where only load and store access memory, and a large register set often organized into register windows to reduce memory access; this enables simple hardware, single-cycle execution, and effective pipelining. The fundamental trade-off is between code density (CISC) and execution speed/simplicity (RISC). The MC68000 has separate data and address registers, while SPARC uses register windows to manage function calls efficiently.

🧠 Quick Revision Questions

1. What are the key differences in instruction length between the MC68000 (CISC) and SPARC (RISC)?
2. Explain the load/store architecture used in RISC, and give one reason why it benefits pipeline performance.
3. What is the purpose of register windows in the SPARC architecture?
4. In the MC68000, what does the instruction MOVE.L (A0)+, D0 do, and how does it illustrate CISC philosophy?
5. Why might a RISC program require more instructions than a CISC program to perform the same task, and yet still be faster overall?

📘 Lecture 12 — CPU Design

📖 Overview: This lecture explores the central processing unit design from the logic designer’s perspective, focusing on converting behavioral RTL into concrete structural RTL. It examines the uni-bus implementation of the SRC processor, detailing data path design, control unit design, and structural RTL descriptions for various instruction types, providing a foundation for understanding processor architecture implementation.

🗂️ Topics Covered

The lecture covers the complete processor design process, beginning with ISA design through behavioral and structural RTL descriptions. It examines the uni-bus data path implementation for the SRC processor, including all major components like the register file, MAR, MBR, PC, IR, registers A and C, and the ALSU. Detailed structural RTL descriptions are provided for instruction fetch, arithmetic/logic instructions (including register-to-register sub, add, not, and immediate operations), as well as load and store instructions, with timing step requirements for each.

📝 Lecture Summary

The design process

The processor design process begins with the specification of behavioral RTL for its instruction set. This abstract description is then converted into structural RTL which shows actual implementation details. Since the processor divides into two main sub-systems—the data path and the control unit—the design procedure splits into two phases: data path design and control unit design.

💡 Why this matters: The design activity must consider pros and cons of different approaches, as execution time depends on three factors: ET = IC × CPI × T (Execution Time = Instruction Count × Cycles Per Instruction × Clock cycle Time). Implementation details affect CPI and clock cycle time, so designers must consider effect on overall performance, amount of control hardware, and development time.

🔑 Definition — Behavioral RTL: A register transfer language description of processor behavior in response to specific instructions, not bound to any specific implementation, presenting only static (registers) and dynamic aspects (operations) necessary to understand functionality.

🔑 Definition — Structural RTL: A register transfer language description formed according to the proposed micro-architecture, showing actual implementation steps including hidden temporary registers necessary for instruction execution, satisfying time and space requirements specified by clocking interval and number of registers and buses.

Processor Design

The processor design procedure involves five steps:

1. ISA Design: Specification of the instruction set including decisions about number and size of instructions, formats, addressing modes, memory organization, and programmer’s view of CPU (number and size of general and special purpose registers).

2. Behavioral RTL Description: Describes processor behavior in register transfer language, where the unit of activity is instruction execution (unlike clock cycle in actual case).

3. Implementation of the Data Path: Involves decisions about placement and interconnection of registers, type of flip-flops, number and kind of interconnection buses. All decisions affect number and speed of register transfers during operations. The structure of ALU and memory-to-CPU interface are also decided here.

4. Structural RTL Description: In accordance with chosen data path implementation, structural RTL for every instruction is described, satisfying time and space requirements.

5. Control Unit Design: Involves timing and synchronization issues plus combinational logic. Approaches include hard-wired or micro-programmed control. Steps include: a) Analyze structural RTL and prepare list of control signals; b) Develop logic circuits for control signals; c) Tie everything together.

A Uni-bus Data Path Implementation for the SRC

The Data Path: The data path is the arithmetic portion of the Von Neumann architecture, consisting of registers, internal buses, arithmetic units, and shifters. The 1-Bus SRC data path employs a single bus for data flow.

The following units are present in the SRC data path:

1. The Register File: The general-purpose register file includes 32 registers R0 to R31, each 32-bit wide. These registers communicate with other components via the internal processor bus.

2. MAR: The Memory Address Register takes input from the ALSU as the address of the memory location to be accessed and transfers memory contents onto the memory sub-system.

3. MBR: The Memory Buffer Register has a bi-directional connection with both the memory sub-system and the registers and ALSU. It holds data during transmission to and from memory.

4. PC: The Program Counter holds the address of the next instruction to be executed. Its value is incremented after loading each instruction and can be changed based on branch decisions in ALSU. It has a bi-directional connection with the internal processor bus.

5. IR: The Instruction Register holds the instruction being executed. Instruction fields are extracted from IR and transferred to appropriate registers according to external circuitry.

6. Registers A and C: Required to hold an operand or result value while the bus is busy transmitting some other value. Both registers are programmer invisible.

7. ALSU: A 32-bit Arithmetic Logic Shift Unit that takes input from memory or registers via the bus, computes results according to control signals, and places result in register C for final transfer to destination.

Timing Step Generator: A timing device that provides mutually exclusive and sequential timing intervals (analogous to clock cycles in actual processor). Each mutually exclusive step is carried out in one timing interval, named T0, T1...T7.

Structural RTL descriptions of selected SRC instructions

Structural RTL for Instruction Fetch: Takes three time steps:

• T0: Address of instruction is moved to MAR and PC value is incremented
• T1: Instruction is brought from memory into MBR, and incremented PC is updated
• T2: Instruction from MBR is written into IR for execution

What follows is the instruction execution phase. The number of timing steps depends on instruction type and complexity.

Structural RTL for Arithmetic/Logic Instructions: Come in two formats—immediate operand and register operand.

Register-to-Register sub: sub ra, rb, rc takes three timing steps:

• T3: Register A receives contents of register rb
• T4: Value of register rc is subtracted (since op-code is sub) from A
• T5: Result is transferred into destination register ra

💡 Why this matters: Control signals must be applied to the ALSU based on decoding the op-code field of an instruction. ALSU functions use uppercase names (e.g., SUB, ADD) to differentiate from actual operation-code mnemonics. Functions SHL, SHR, SHC, and SHRA assume a barrel shifter is available.

Structural RTL for Register-to-Register add: add ra, rb, rc:

• T0-T2: Instruction fetch (common to all instructions)
• T3: First operand moved to register A
• T4: Computation of sum
• T5: Result transferred to destination

Complete execution takes 6 time steps. Other arithmetic/logic instructions like sub, and, and or have similar structural RTL, differing only in T4 step where sign changes to (-), (^), or (~) according to opcode.

Structural RTL for the not instruction: not ra, rb:

• T0-T2: Instruction fetch
• T3: Operand value brought into ALSU, which uses control function NOT, negates (inverts) the value, result moves to register C
• T4: Result assigned to destination register through internal bus

Control signals needed: signal to allow reading of instruction-specified source register in T3, signal for ALSU function selection, and signal to allow only instruction-specified destination register to read result from data bus.

Structural RTL for the addi instruction:

• T0-T2: Instruction fetch
• T3: First operand brought into ALSU through register A
• T4: Second operand c2 extracted from IR register, sign extended to 32 bits, added to first operand, written into result register C
• T5: Result written into destination register

Sign extension is assumed to be carried out in the ALSU. Sign extension for 17-bit c2: (15αIR<16> ©IR<16..0>). Sign extension for 22-bit c1: (10αIR<21> ©IR<21..0>). Other instructions with same structural RTL: subi, andi, and ori.

RTL for the load (ld) and store (st) instructions: Syntax for load: ld ra, c2(rb). Syntax for store: st ra, c2(rb).

First 6 time steps (T0 to T5) are the same for both:

• T0-T2: Instruction fetch
• T3: Register A gets value of register rb (if not zero)
• T4: Constant is sign-extended and added to register A value using ALSU, result assigned to register C
• T5: Value in C transferred to MAR (completes effective address calculation)

For load instruction:

• T6: Corresponding memory location accessed, result stored in MBR
• T7: Result transferred to destination register ra using data bus

For store instruction:

• T6: Value of register stored to MBR
• T7: Value in MBR stored in memory location indexed by MAR

If more time steps are required, a counter with more bits and larger decoder can be used (e.g., 4-bit counter with 4-to-16 decoder can produce up to 16 time steps).

⭐ Key Takeaways

The processor design process follows a sequential flow from ISA specification through behavioral RTL to structural RTL, then data path implementation and control unit design. The uni-bus SRC implementation uses a single bus connecting all major components (register file, MAR, MBR, PC, IR, registers A and C, ALSU) with a timing step generator providing mutually exclusive timing intervals. Instruction fetch always requires three timing steps (T0-T2), while execution timing varies by instruction complexity—arithmetic/logic instructions typically take three execution steps, while load/store instructions require more (up to T7). The key difference between load and store instructions occurs after effective address calculation: load reads memory into MBR then transfers to destination register, while store moves register value to MBR then writes to memory. Control signals must be carefully designed based on op-code decoding to coordinate all data path operations across the appropriate timing steps.

🧠 Quick Revision Questions

1. What are the five steps in the processor design procedure, and what is the main output of each step?

2. In the uni-bus SRC data path, which registers are programmer visible and which are programmer invisible?

3. How many timing steps does the instruction fetch phase require, and what happens in each step?

4. What is the difference in structural RTL between a load instruction (ld) and a store instruction (st) during steps T6 and T7?

5. How does sign extension work for the 17-bit c2 and 22-bit c1 fields in immediate instructions, and where is this operation performed?

📘 Lecture 13 — Structural RTL Description of the FALCON-A

📖 Overview: This lecture continues the structural RTL description of the SRC processor and introduces the structural RTL for the FALCON-A processor. It covers branch, shift, arithmetic, logical, and memory instructions in detail, highlighting the differences in data path width, register size, and number compared to SRC. Understanding these RTL descriptions is crucial for processor design and implementation.

🗂️ Topics Covered

The lecture covers Structural RTL for branch instructions (brzr, brlzr), Structural RTL for shift instructions, Structural RTL Description of FALCON-A Instructions including uni-bus data path implementation, ALSU functions needed, and structural RTL for subtract, addition, multiplication, division, not, add immediate, load/store, and conditional jump instructions. It also explains sign extension for immediate constants and the need for additional registers (AH, CH) for multiplication and division operations.

📝 Lecture Summary

Structural RTL for branch instructions

The lecture examines the structural RTL for branch instructions, including unconditional and conditional branches. The branch if zero (brzr) instruction brzr rb, rc instructs the processor to branch to the instruction at the address held in register rb if the value stored in register rc is zero. The first three steps are for instruction fetch, then the value of register rc is checked and the condition flag CON is set. In time step T4, the program counter is set to the register rb value depending on the CON bit.

🔑 Definition — brzr (branch if zero): A conditional branch instruction that branches to the address in register rb if register rc contains zero.

The branch and link if zero (brlzr) instruction brlzr ra, rb, rc is the same as brzr but additionally saves the return address. The steps are the same as brzr with an additional step after the condition bit is set: the current value of the program counter is saved to register ra, implementing the linking procedure.

🔑 Definition — brlzr (branch and link if zero): A conditional branch instruction that branches to the address in register rb if register rc contains zero, and saves the return address in register ra.

Structural RTL for shift instructions

Shift instructions are complicated because they require extra hardware to hold and decrement the count. For an ALSU that can perform only single bit shifts, data must be repeatedly cycled through the ALSU and the count decremented until it reaches zero, creating timing problems. These problems can be overcome by employing multiple-bit shifts using a barrel shifter. The structural RTL for shr ra, rb, rc or shr ra, rb, c3 uses n representing a 5-bit register where IR bits 0 to 4 are copied into it. N is the decimal value of the number in this register. The actual shifting occurs in step T5. Other instructions with similar tables are: shl, shc, shra — for example, for shra, T5 will have C← (NαR [rb] <31>) © R[rb] <31...N>.

🔑 Definition — Barrel shifter: A hardware component that can perform multiple-bit shifts in a single clock cycle, overcoming timing problems associated with single-bit shift operations.

Structural RTL Description of FALCON-A Instructions

Uni-bus data path implementation

Comparing the uni-bus implementation of FALCON-A with that of SRC results in several differences:

• FALCON-A processor bus has 16 lines (16-bits wide) while SRC is 32-bits wide
• All registers of FALCON-A are 16-bits while SRC registers are 32-bits
• Number of registers in FALCON-A is 8 while SRC has 32 registers
• Special registers (PC and IR) are 16-bit registers in FALCON-A (32-bit in SRC)
• MAR (Memory Address Register) and MBR (Memory Buffer Register) are 16-bits in FALCON-A (32-bit in SRC)
• MAR and MBR are dual port registers — connected to internal bus on one side and external memory on the other side, to point to a particular address for reading or writing data from or to memory

💡 Why this matters: The reduced bus width and register size in FALCON-A make it a simpler, smaller processor compared to SRC, suitable for embedded or cost-sensitive applications.

ALSU functions needed

The ALSU of FALCON-A has slightly different functions. Two significant instructions are mul and div. When one of these instructions is activated, the ALSU unit takes the operand from its input and provides the output immediately (neglecting propagation delays). FALCON-A has two registers A and AH, each of 16-bits. AH contains the higher 16-bits (most significant) of a 32-bit operand, providing the facility of using 32-bit operands in certain instructions. At the output of ALSU, a 32-bit result needs to be saved in two registers: C and CH where CH stores the most significant 16-bits of the result.

🔑 Definition — AH (Accumulator High): A 16-bit register in FALCON-A that contains the most significant 16-bits of a 32-bit operand. 🔑 Definition — CH (C High): A 16-bit register in FALCON-A that stores the most significant 16-bits of a 32-bit ALSU result.

Why do we need to add AH and CH?

These registers are needed because FALCON-A has mul and div instructions. For div instruction, at the input, one operand (the dividend) would be 32-bits. For mul instruction, the output (result of multiplying two 16-bit numbers) would be 32-bit, placed in C and CH. Data in these two registers will be concatenated, and the input operand is in two registers AH and A. Conceptually, A and AH together represent a 32-bit operand.

Structural RTL for subtract instruction

The sub ra, rb, rc instruction involves three registers. The first three steps fetch the instruction, and in T3, T4, T5 the execution steps are performed.

Structural RTL for addition instruction

The add ra, rb, rc instruction table is almost the same as sub instruction except in timing step T4 we have + sign for addition instead of - sign. Other instructions that belong to the same group are and, or, and sub.

Structural RTL for multiplication instruction

The mul ra, rb, rc instruction is only present in FALCON-A, not in SRC. The first three steps fetch the instruction. In step T3, contents of register R[rb] are brought into buffer register A at the input of ALSU. In step T4, multiplication of A with contents of R[rc] is performed and the result is placed at the output in two registers C and CH — CH contains the higher 16-bits, C contains the lower 16-bits. These two registers cannot transfer data in one bus cycle (width is 16-bits), so two timing steps are needed: in T5 the higher byte is transferred to register R[0], and in T6 the lower 16-bits are transferred to the placeholder R[a]. The multiplication instruction requires 3 timing steps for Instruction Fetch and 4 timing steps for Instruction Execution, totaling 7 steps.

Structural RTL for division instruction

The div ra, rb, rc instruction has the first three steps the same. In step T3, contents of register rb are placed in buffer register A. In step T4, contents of register R[0] are taken into register AH (assuming higher 16-bits of dividend are placed in R[0] before using the divide instruction). In T5, actual division takes place in two concurrent operations. The dividend at the input of ALSU is represented by concatenation of AH and A. The first operation takes the remainder (AH concatenated with A divided by contents of register rc), placed in register CH. The quotient is placed in C. In T6, C is taken to register R[ra]. In T7, the remainder in CH is taken to default register R[0] through the bus. The divide instruction requires 5 timing steps to execute and 3 to fetch.

🔑 Note: For mul and div instructions, register R[0] must be properly loaded prior to use. For example, in the divide instruction, if appropriate data is not available in R[0], the result would be wrong.

Structural RTL for not instruction

The not ra, rb instruction has the first three steps fetching the instruction. In T3, the not operation (one's complement: changing 0's to 1's and 1's to 0's) is performed on contents of R[rb] and transferred into buffer register C. In timing step T4, contents of register C are transferred to register R[ra] through the bus.

Structural RTL for add immediate instruction addi ra, rb, c1

In this instruction, c1 is a constant part of the instruction. First three steps are for Instruction Fetch. In T3, contents of register R[rb] are taken into buffer register A. In T4, contents of A are added with constant c1 after sign extension and brought to C.

Sign extension of 5-bit c1 and 8-bit constant c2

Sign extension for 5-bit c1 is: (11αIR<4> ©IR<4.. 0>) — the immediate constant c1 is in the lower 5-bits, bit number 4 indicates the sign bit, which is copied to the leftmost 11 positions to make a 16-bit number.

Sign extension for 8-bit c2 is: (8αIR<7> ©IR<7.. 0>) — the sign bit is placed to the leftmost 8 positions to make a 16-bit number.

📐 Formula — Sign extension for 5-bit constant: (11αIR<4> ©IR<4.. 0>) → copies bit 4 (sign bit) to the 11 leftmost positions to create a 16-bit number. 📐 Formula — Sign extension for 8-bit constant: (8αIR<7> ©IR<7.. 0>) → copies bit 7 (sign bit) to the 8 leftmost positions to create a 16-bit number.

Structural RTL for the load and store instruction

Tables for load and store instructions are the same as SRC except a slight difference in notation. When square brackets [R[rb]+c1] appear, it corresponds to the base address in R[rb] and an offset taken from c1.

Structural RTL for conditional jump instructions

The jz ra, [c2] instruction (jump if zero) has the first three steps fetching the instruction. In T3, a 1-bit register CON is set to true if the condition is met. The condition is tested by the contents given by register ra. The condition is R[ra], meaning test the data in register ra. Data could be positive, negative, or zero. For this instruction, it tests if data is zero — if zero, CON would be 1.

In T4, contents of the PC are taken into buffer register A. In T5, contents of A are added to constant c2 after sign extension, giving the effective address for the jump. In T6, this value is copied to the PC.

In FALCON-A, the number of conditional jumps is more than in SRC. Examples include:

• jz (op-code=19) jump if zero: jz r3, [4] (R[3]=0): PC← PC+2
• jnz (op-code=18) jump if not zero: jnz r4, [variable] (R[4]≠0): PC← PC+variable
• jpl (op-code=16) jump if positive: jpl r3, [label] (R[3]≥0): PC ← PC+(label-PC)
• jmi (op-code=17) jump if negative: jmi r7, [address] (R[7]<0): PC← PC+address

The unconditional jump instruction will be explained in the next lecture.

⭐ Key Takeaways

The structural RTL for FALCON-A differs significantly from SRC in bus width (16-bit vs 32-bit), register count (8 vs 32), and register size (16-bit vs 32-bit). The multiplication and division instructions require additional registers AH and CH to handle 32-bit operands and results, along with extra timing steps for data transfer due to the narrower bus width. Sign extension of immediate constants (5-bit c1 and 8-bit c2) is critical for correct arithmetic operations with immediate values. Conditional jumps test a flag register CON based on the contents of a specified register, and jump instructions require multiple steps to compute the effective address and update the program counter. Register R[0] plays a special role in storing high-order bits for division and multiplication operations, and must be properly initialized before use.

🧠 Quick Revision Questions

1. What are the key differences between FALCON-A and SRC processor implementations in terms of bus width, register count, and register size?
2. Why are the additional registers AH and CH needed in FALCON-A, and how are they used in the mul and div instructions?
3. Describe the timing steps for the branch and link if zero (brlzr) instruction, including how the return address is saved.
4. What is the sign extension process for a 5-bit constant c1, and why is it necessary in the addi instruction?
5. How does the conditional jump instruction jz work, including how the CON flag is set and how the effective address is computed?

📘 Lecture 14 — External FALCON-A CPU

📖 Overview: This lecture continues the structural RTL description of the FALCON-A CPU, covering unconditional jump, shift, mov, call, ret, in, and out instructions. It then examines the external FALCON-A CPU interface, including control signals and bus activity, and provides an example problem to demonstrate how to determine bus logic levels and addressing modes during instruction execution.

🗂️ Topics Covered

The lecture covers the structural RTL for unconditional jump, shift (shiftr, shiftl, asr), mov, movi, in, out, call, and ret instructions. It details control signals required at different timing steps during instruction fetch and execution. It then introduces the external FALCON-A CPU interface with address, data, and control buses. The lecture concludes with an example problem that requires determining address bus, data bus, and control signal values for given instructions using a memory map and register map.

📝 Lecture Summary

Un-conditional jump instruction (op-code=20)

The unconditional jump instruction with op-code 20 is followed by a 3-bit identifier for register ra and an 8-bit constant c2.

📐 Formula: For jump [ra + constant], (ra=0): PC ← PC + (8αC2<7>)©C2<7..0>, (ra≠0): PC ← R[ra] + (8αC2<7>)©C2<7..0>

The assembler allows forms: jump [ra + constant], jump [ra + variable], jump [ra + address], jump [ra + label]. The jump range is –128 to 127 due to the 8-bit constant c2. The target address must be even because each instruction is 2 bytes. Types of unconditional jumps include direct, indirect, PC-relative, and register relative. When ra=0, it is a PC-relative near jump; when ra≠0, it is a register-relative far jump.

Structural RTL description for unconditional jump instruction (jump [ra+c2])

In steps T0-T2, the jump instruction is fetched. In T3, if ra field is zero, the contents of PC are placed in temporary register A; otherwise, the contents of register ra are placed in A. The comma indicates these are concurrent, and only one executes. In T4, the constant c2 is sign-extended and added to the contents of A, placing the effective address in buffer register C. In T5, the contents of C are loaded into PC.

💡 Why this matters: Understanding this RTL sequence explains how both PC-relative and register-relative jumps are implemented using a single set of hardware steps.

Structural RTL for the shift instruction (shiftr ra, rb, c1)

First three steps fetch the shift instruction. c1 is a 5-bit constant from the lower 5 bits of the instruction register IR. In T3, the 5-bit register ‘n’ is loaded from the count field. In T4, depending on ‘N’ (the decimal value of ‘n’), the contents of register rb are shifted right by N bits. Zeros are replicated N times and concatenated with the shifted bits (15...N). In T5, the contents of C are transferred to destination register ra.

For shiftl and asr, similar tables apply. In asr (arithmetic shift right), instead of copying zeros, the sign bit from the original data is copied to the leftmost position.

🔑 Definition — ‘n’ vs ‘N’: ‘n’ indicates the register storing the count; ‘N’ indicates the decimal value of the bits in register ‘n’.

Other instructions: mov, call, ret

These instructions were not available in the SRC processor.

Structural RTL for the mov instruction (mov ra, rb)

Data in register rb (source) is moved to register ra (destination). In steps T0-T2, the mov instruction is fetched. In T3, the contents of register rb are placed in buffer register C through the ALSU unit. In T4, buffer register C transfers data to register ra through the internal uni-bus.

Structural RTL for the mov immediate instruction (movi ra, c2)

Constant c2 is moved into destination register ra. First three steps fetch the move immediate instruction. In T3, constant c2 is placed into buffer register C. Since C is 16-bit and c2 is 8-bit, the remaining leftmost bits are concatenated with the sign bit (bit <7>). If the number is negative, sign bit is ‘1’; if positive, sign bit is ‘0’. In T4, the contents of C are taken to destination register ra.

Structural RTL for the in instruction (in ra, c2)

FALCON-A has ‘in’ and ‘out’ instructions not present in SRC. For FALCON-A, assume interconnection with input and output addresses up to 0..255.

First three steps fetch the instruction. In T3, IO[c2] indicates going to the IO address specified by c2 (a positive constant), and data is taken to buffer register C. In T4, data is transferred from C to destination register ra.

Structural RTL for the out instruction (out ra, c2)

This is opposite to the ‘in’ instruction. First three instructions fetch the instruction. In T3, contents of register ra are placed into buffer register C. In T4, data from C is placed at the output port indicated by constant c2.

Structural RTL for the call instruction (call ra, rb)

Control is given to a procedure, subroutine, or another address. First three steps fetch the call instruction. In T3, the present contents of PC are stored in buffer register C. In T4, data from C is transferred to register ra, which will contain the original PC contents (a return pointer). In T5, contents of register rb (the target address) are placed in C. In T6, contents of C are placed in PC, so PC indicates the new execution position.

💡 Why this matters: The call instruction saves the return address in ra before jumping to the subroutine address in rb, enabling proper return after subroutine completion.

Structural RTL for return instruction (ret ra)

After instruction fetch in steps T0-T2, the register data in ra is placed in buffer register C through the ALSU unit. In T4, PC is loaded with the contents of this buffer register.

Control signals required at different timing steps of FALCON-A instructions

The table shows time steps, structural RTLs, and corresponding control signals. In step T0, the internal bus is active, placing PC contents in MAR while PC is incremented by 2 and placed in C. Control signals: LMAR enables writing to MAR; PCout makes PC contents available; INC2 increments PC; LC writes data from ALSU output to buffer register C.

In T1, data from memory location addressed by MAR is read into MBR. MARout enables the MAR tri-state buffer; MRead enables memory read; Cout enables buffer register C to provide data to bus; LPC enables PC to read from C; LMBR enables reading data from memory into MBR.

In T2, IR is loaded with data from MBR. Control signals: MBRout enables MBR tri-state buffers; LIR is the load signal for IR register.

In SRC, the fetch operation uses INC4 instead of INC2 because the instruction length is 4 bytes. For all instructions, the fetch cycle is the same; execution phase control signals vary per instruction.

💡 Why this matters: Understanding control signals is essential for knowing which operations occur at each timing step and for designing the control unit.

External FALCON-A CPU Interface

The processor generates control signals used by memory or I/O to read/write data. The external interface consists of:

• 16-bit address bus
• 16-bit data bus
• Control bus with signals: MRead, MWrite, IORead, IOWrite

It is assumed that memory read is fast enough, so data is available in a fixed time interval (T2 in this example). For slow data transfer, handshaking with idle states would be used.

Example Problem

Given: PC = C348h, memory storage is big-endian, memory contents are properly aligned, a memory map and register map are provided.

(a) Determine logic levels on external FALCON-A buses for each instruction. (b) Specify memory-addressing modes.

Solution for Load instruction (RTL: MAR ← R[5] + 12, MBR ← Mem[MAR], R[3] ← MBR):

• Address bus: Contents of r5 (1234h) + 12 decimal (Ch) = 1240h
• Data bus: Contents of memory location 1240h (from memory map) = 785h
• Control signals: MRead = 1, MWrite = 0

For instruction involving only registers: No external bus activity, so address bus, data bus, and control bus columns contain ‘?’ or are unknown.

For Jump instruction (PC ← PC + offset 52): External bus remains inactive, control signals are zero.

For Store instruction (RTL: MAR ← R[3] + 17, Mem[MAR] ← R[6]):

• This is a memory write operation: MWrite = 1, MRead = 0
• Effective address = R[3] contents + 17 decimal
• Convert 17 to hex (11h), add to R[3] contents (from register map) to get address

Addressing Modes

The table lists the addressing mode for each instruction in the example, based on how the effective address is computed.

⭐ Key Takeaways

The FALCON-A CPU extends the SRC instruction set with in, out, mov, call, and ret instructions, each with specific structural RTL descriptions. All instructions share a common three-step fetch cycle (T0-T2) with specific control signals (PCout, LMAR, INC2, LC, Cout, LPC, MRead, LMBR, MBRout, LIR). The jump instruction uses sign-extended 8-bit constant c2, with PC-relative (ra=0) or register-relative (ra≠0) addressing. The external CPU interface includes a 16-bit address bus, 16-bit data bus, and control signals (MRead, MWrite, IORead, IOWrite). For exam problems involving memory maps and register maps, it is critical to determine address bus values by adding register contents to displacements (converted to hex), data bus values from memory contents at that address, and appropriate control signals for read vs. write operations.

🧠 Quick Revision Questions

1. For the jump instruction [ra + c2], what determines whether the jump is PC-relative or register-relative?
2. Write the structural RTL steps T3-T5 for the shiftr instruction, explaining what happens in each step.
3. What three control signals are activated in step T0 of the fetch cycle, and what does each accomplish?
4. In the external FALCON-A interface, what are the sizes of the address bus and data bus, and what control signals are present?
5. For a store instruction with R[3] = C2EFh and displacement = 17 decimal, what is the effective address placed on the address bus?

📘 Lecture 15 — Logic Design and Control Signals Generation in SRC

📖 Overview: This lecture focuses on the logic design for the uni-bus SRC, detailing the control signals necessary for instruction fetch and execution. It explores how the control path ensures synchronized operation of the data path components, includes external CPU interface details, and provides examples to solidify understanding of control signal generation.

🗂️ Topics Covered

The lecture covers identifying control signals for the fetch operation, the uni-bus SRC implementation with external CPU bus activity, memory address register (MAR) and memory buffer register (MBR) circuitry, register connections and alternate control circuitry, control signals for specific instructions like add, addi, and ld, and the process of sign extension.

📝 Lecture Summary

Logic Design for the Uni-bus SRC

This section bridges behavioral and structural RTL by introducing the control path. The control unit generates signals to coordinate the data path's components, ensuring instructions execute correctly. Key topics include identifying control signals, the external CPU interface, MAR/MBR circuitry, register connections, and sign extension. These elements work together to enable smooth, consistent operations in the SRC.

Identifying control signals

Control signals are required for every instruction in the SRC's instruction set. They select ALU functions, registers, or memory locations. For the fetch operation, control signals are issued in sequence during time slots T0, T1, and T2, with signals in each slot activating simultaneously.

Control signals for the fetch operation (Table 1): In T0, PCout writes the Program Counter to the internal bus, LMAR loads it into the Memory Address Register, INC4 increments PC by 4 in the ALSU (result stored in C), and LC enables writing to register C. In T1, LMBR enables writing to the MBR from the bus, MRead gates memory data into MBR, MARout enables MAR's tri-state buffers to the address bus, Cout writes register C onto the bus, and LPC loads the incremented value into PC. In T2, MBRout enables MBR output, and LIR loads the instruction into the Instruction Register.

Uni-bus SRC implementation

The uni-bus data path (Fig. 1) uses these control signals in mutually exclusive time steps for the instruction fetch cycle. Similar signals handle instruction execution. The external CPU interface includes address/data buses and memory read/write control signals. 💡 Why this matters: This implementation shows how control signals coordinate all components to fetch and execute instructions correctly.

Example problem with Table 2: Given PC = 000DC348h, memory map (Fig. 3), and register map (Fig. 4), the solution (Fig. 5) determines logic levels on external buses for instructions like ld, add, st, and beq. Part (b) specifies addressing modes (e.g., ld uses displacement, add uses register, st uses displacement, beq uses PC-relative). Notes: Relative addressing is always PC-relative; displacement is same as based/indexed/register relative.

MAR circuitry (Fig. 6): MAR loads from the internal CPU bus via LMAR and drives the external address bus via MARout, which controls tri-state buffers. It stores addresses for memory/I/O access.

MBR circuitry (Fig. 7): MBR loads from the internal bus or external data bus, and drives both buses. Tri-state buffers are at connection points. It holds data read from or to be written to memory.

Register connections (Fig. 8): The register file with general-purpose registers is programmer-visible. ra, rb, rc fields from the IR specify registers. Control signals RAE, RBE, RCE select a field for a 5-to-32 decoder, outputting a signal for the specific register. BUS2R enables writing to a register from the bus, and R2BUS enables reading a register onto the bus.

Alternate control circuitry for register selection (Fig. 9): This implementation uses a separate 5-to-32 decoder for each register field (ra, rb, rc). Decoder outputs enable the decoded register if RAE, RBE, or RCE is active. It illustrates multiple design possibilities.

Control signals Generation in SRC

Control signals for the add instruction: add ra, rb, rc. Table 4 lists signals per time step. In T3: RBE selects rb, R2BUS reads it to bus, LA writes to register A. In T4: RCE selects rc, R2BUS reads it, ADD selects add function in ALSU, LC writes result to C. In T5: Cout reads C, RAE selects ra, BUS2R writes result to ra.

Sign extension: When copying constant values to 32-bit registers, sign extension copies the most significant bit (MSB) to all additional leftmost bits. For the 17-bit constant c2, bus bits 31-17 become c2<16>. A 15-line tri-state buffer performs this (Fig. 10), with c2<16> applied to all its inputs.

🔑 Definition — Sign extension: Copying the MSB of a number to all additional bits when widening its representation in 2's complement form. 📐 Formula: bus<31:17> = c2<16> → "The high-order bits of the bus equal the sign bit of the constant." 📌 Example: Extend c2 = 0b1_0000_0000_0000_0001 (17-bit, negative) to 32 bits: new value = 0b1111_1111_1111_1111_1000_0000_0000_00001.

Structural RTL for the addi instruction: addi ra, rb, c2. Control signals (Table 5) are same as add, except in T4: c2out enables the sign-extended constant onto the bus, ADD adds, LC stores result in C.

To place a 0 on the bus: When rb field is 0 (e.g., in ld and st instructions), the circuit (Fig. 11) outputs a hardwired 0 from a tri-state buffer onto the bus, rather than enabling register R0's output. An alternate circuit (Fig. 12) does the same.

Control signals for the ld instruction: ld ra, c2(rb). Table 6 shows RTL and signals. Steps T0-T2 are fetch. In T3: RBE, R2BUS, LA load rb into A. In T4: c2out, ADD, LC compute effective address in C. In T5: Cout, LMAR load MAR with the address. In T6: MARout outputs address, MRead reads memory, LMBR loads data into MBR. In T7: MBRout reads MBR to bus, RAE selects ra, BUS2R writes loaded data to ra.

⭐ Key Takeaways

For the exam, you must remember the sequence of control signals for instruction fetch and specific instructions like add, addi, and ld. Understand the roles of MAR and MBR in memory access and how tri-state buffers enable bus sharing. Sign extension is critical for handling constant values, and special circuits place zero on the bus when the rb field is zero. The control signals (e.g., PCout, LMAR, R2BUS) always follow a strict timing order across T0-T7.

🧠 Quick Revision Questions

1. What are the control signals issued during time step T0 of the instruction fetch phase, and what does each do?
2. In the add instruction, which control signals are activated at time step T4, and what is their purpose?
3. How does the sign extension of the constant c2 work in the SRC?
4. What is the difference in control signals between the add and addi instructions?
5. List the control signals for the ld instruction at time steps T5, T6, and T7, explaining each action briefly.

📘 Lecture 16 — Control Unit Design

📖 Overview: This lecture continues the discussion of control signal generation for SRC instructions, covering store, branch, branch-and-link, and shift instructions. It then introduces the control unit’s role in generating timing and control signals, compares hardwired versus microprogrammed design approaches, and presents a 2-bus implementation of the SRC data path.

🗂️ Topics Covered

Control signal generation for the store instruction, branch and branch-link instructions, and the shift right instruction are detailed. The control unit’s design is then examined, focusing on its inputs, the hardwired approach using Boolean equations, and the effect of real gate propagation delays. Finally, the 2-bus SRC data path implementation and its structural RTL are presented.

📝 Lecture Summary

Control Signals Generation in SRC (continued...)

The lecture continues from the previous one, detailing additional control signals. For the store instruction st ra, c2(rb), the time step operations are similar to the load instruction, with differences in steps T6 and T7. The control signals for branch instructions like brzr rb, rc involve the LCON signal to enable the condition (CON) circuitry, RCE to read the register rc, and R2BUS to allow the bus to read from the selected register. At step T4, RBE reads the register rb (the branch target address) and LPC is issued conditionally (if CON=1) to update the program counter. For branch and link instructions like brlzr ra, rb, rc, an additional step T4 is used for the link operation, shifting the simple branch’s T4 to T5. For the shift right instruction shr, the five bits of n are applied to the select inputs of the barrel shifter, and the control signal SHR is activated.

The Control Unit

The control unit (CU) generates both control signals and timing signals, synchronizing internal and external events. It instructs the data path on what to do every clock cycle during instruction execution. CU design is critical, as most processor errors occur here. Two primary design approaches exist:

1. Hardwired approach: Faster but complex circuitry.
2. Microprogrammed approach: Slower but more flexible.

Finite-state machine concepts represent the CU, with each state corresponding to one clock cycle (timing step). The CU has four sets of inputs:

1. Output of the timing step generator (T0-T7).
2. Op-code (decoded from the Instruction Register).
3. Data path generated signals (e.g., CON).
4. Signals from external events (e.g., Interrupt).

The complexity of the control unit depends on the number of states, number of inputs, and number of outputs.

Hardwired Implementation of the Control Unit

In hardwired implementation, the operation code (op-code) field of the Instruction Register is decoded. For a processor like the FALCON-A with a 16-bit instruction, the 5 most significant bits (or IR<31..27> for the 32-bit SRC) are fed to a 5-to-32 decoder. Only one of the 32 outputs (op0 to op31) is active at a time, corresponding to the executing instruction.

To design the CU, Boolean equations are written by browsing structural descriptions to see which control signals appear in different timing steps. Each instruction has a table defining structural RTL and control signals. The equation is a logical combination (AND and OR) of control signals. For example, the equation for PCout is: PCout = T0 + T3.(OP20 + OP22) + T4.(OP16 + OP17 + OP18 + OP19) This means PCout is active in T0 always, OR in T3 if the op-code is 20 or 22 (jump/subroutine call), OR in T4 if the op-code is 16-19 (conditional jumps). Similarly, the equation for LPC is: LPC = T1 + T5.OP20 + T6.CON.(OP16 + OP17 + OP18 + OP19) These equations are implemented using logic circuits with AND/OR gates.

🔑 Definition — CON: A control signal that is set to 1 only if the specified condition for a conditional branch is met.

📌 Example: The logic circuit for PCout combines T0, T3 ANDed with OR of OP20 and OP22, and T4 ANDed with OR of OP16 through OP19, all ORed together.

💡 Why this matters: These Boolean equations form the blueprint for the physical logic gates in the control unit.

Effect of using “real” Gates

In real circuits, gates have propagation delays, and cascading gates adds delays. This places an upper limit on the clock frequency controlling timing intervals (T0-T7). For example, transferring contents of register R1 to R2 requires a minimum time t_min, so the maximum clock frequency is 1/t_min. Students are encouraged to study the text’s Example 4.1.

2-Bus Implementation of the SRC Data Path

The 2-bus SRC data path has an ‘in’ bus for writing data to components and an ‘out’ bus for reading data from components. The structural RTL for the sub instruction using this implementation is illustrated. The first three steps are for instruction fetch; at step T3, register R[rb] is written to register A. At step T4, the subtracted result from the ALSU is assigned to register R[ra], requiring no temporary register due to the two buses.

📐 Formula: Result = R[ra] ← R[rb] - R[rc] (for the sub instruction).

Control signals for the fetch operation

The control signals for the instruction fetch phase are the same for all instructions.

At time step T0:

• PCout: Enables read of Program Counter onto the ‘out’ bus.
• LMAR: Loads the Memory Address Register.
• C=B: Copies value from ‘out’ bus to ‘in’ bus for loading into MAR.

At time step T1:

• PCout: Value of PC on ‘out’ bus.
• INC4: ALSU performs increment-by-four operation.
• LPC: Enables write of new PC value from ‘in’ bus.
• MRead: Enables memory word read.
• MARout: Supplies address to memory via external bus.
• LMBR: Stores memory word into Memory Buffer Register.

At time step T2:

• MBRout: Reads MBR contents onto ‘out’ bus.
• C=B: Copies value from ‘out’ to ‘in’ bus for loading into MAR.
• LIR: Loads the instruction into the Instruction Register.

At time step T3, execution begins, with control signals depending on the actual instruction. The memory is assumed to be fast enough to respond; if not, wait states are inserted. Control signals within each time slot are activated simultaneously, while those for successive slots are sequential.

⭐ Key Takeaways

The control unit generates all timing and control signals for the processor, with two main design approaches: hardwired (faster, complex) and microprogrammed (slower, flexible). Hardwired design uses Boolean equations derived from RTL descriptions to create logic circuits for each control signal (e.g., PCout, LPC). Real gate propagation delays limit the maximum clock frequency. The 2-bus SRC data path uses separate ‘in’ and ‘out’ buses for efficient data movement, reducing the need for temporary registers during execution. Instruction fetch control signals are consistent across all instructions, while execution-phase signals are instruction-specific.

🧠 Quick Revision Questions

1. What are the four sets of inputs to the hardwired control unit?
2. Write the Boolean equation for PCout in the hardwired control unit and explain each term.
3. Why does the propagation delay of real gates limit the maximum clock frequency?
4. In the 2-bus SRC data path, why is no temporary register needed for the sub instruction at step T4?
5. What is the purpose of the C = B control signal in the 2-bus implementation during instruction fetch?

📘 Lecture 17 — Machine Reset and Machine Exceptions

📖 Overview: This lecture covers two critical mechanisms for controlling processor state: the machine reset operation, which initializes the processor to a known state, and machine exceptions, which interrupt normal instruction flow to handle internal or external events. Both are essential for reliable computer operation, debugging, and system initialization.

🗂️ Topics Covered

The lecture begins with a 3-bus implementation of the SRC data path, showing how instructions like subtract are fetched and executed in two time steps. It then covers the machine reset operation in detail, including behavioral and structural RTL for both hard and soft resets, with a concrete example using the subtract instruction. Finally, it discusses machine exceptions, their processing mechanisms (priority resolution, device identification, state saving), and various types including program exceptions, hardware exceptions, and interrupts.

📝 Lecture Summary

A 3-bus Implementation for the SRC

A 3-bus implementation of the data-path for the SRC is presented, using two buses ‘A’ and ‘B’ for reading, and a bus ‘C’ for writing. All special purpose and general purpose registers have two read ports and one write port in this architecture.

Structural RTL for the Subtract Instruction using the 3-bus Data Path Implementation

The syntax of the subtract instruction is sub ra, rb, rc. The structural RTL for implementing this instruction requires only two time steps for the instruction fetch phase. At time step T0, the Memory Address Register (MAR) receives the value of the Program Counter (PC), then the Memory Buffer Register (MBR) receives the memory word indexed by the MAR, and the PC value is incremented. At time step T1, the instruction register (IR) is assigned the instruction word loaded into the MBR. This concludes instruction fetch. In the next time step, T2, the instruction is executed by subtracting the value of register rc from rb, and assigning the result to register ra. At the end of each sequence, the timing step generator is initialized to T0.

Control Signals for the Fetch Operation

The lecture lists control signals for the instruction fetch phase, noting that control signals for the execute phase can be written similarly.

The Machine Reset

Reset operation The reset operation is required to change the processor's state to a known, defined value. The two essential features are clearing the control step counter and reloading the PC to a predefined value. The control step counter is set to zero so operation restarts from instruction fetch. The PC is reloaded to execute a specific recovery or initializing program.

In most implementations, the reset instruction also clears interrupt enable flags to disable interrupts during initialization. If a condition code register is present, it is usually cleared too. External flags and processor state registers are typically cleared.

The reset instruction is mainly used for debugging purposes, as most processors halt operations immediately or within a few cycles. The processor state may then be examined.

Some processors have two types: Soft reset implies initializing PC and interrupt flags. Hard reset initializes other processor state registers in addition to PC and interrupt enable flags. The software reset instruction asserts the external reset pin.

Reset operation in SRC

Hard Reset: The SRC performs a hard reset upon receiving a start (Strt) signal, initializing PC and general registers.

Soft Reset: The SRC performs a soft reset upon receiving a reset (rst) signal, initializing PC only. The reset signal in SRC is assumed to be external and asynchronous.

PC Initialization: Two approaches exist. The Direct Approach loads the PC with the address of the startup routine upon resetting. The Indirect Approach initializes the PC with the address where the address of the startup routine is located; the reset instruction loads the PC with the address of a jump instruction, which contains the address of the required routine. An example is the 8086 processor, which upon reset initializes PC with address FFFF0H, containing a jump instruction to the bootstrap loader program.

Behavioral RTL for SRC Reset The original behavioral RTL for SRC without reset was: Instruction_Fetch :=(! Run&Strt: (Run ← 1; instruction_Fetch, Run : (IR ← M [PC]; PC ← PC+4; instruction_execution))

The modified RTL after adding reset capability is: Instruction_Fetch:=(! Run&Strt :( Run ← 1, PC, R [0...31] ← 0), Run&!Rst :( IR ← M [PC], PC ← PC+4, instruction_execution); Run&Rst:( Rst ← 0, PC ← 0); instruction_Fetch)

To implement these changes, the following modifications are required: a check for the reset signal on each clock cycle, a control signal for clearing the PC, and a control signal to load zero to the control step counter.

Example: The sub instruction with RESET processing In step T0, if Rst is not asserted, the new instruction address is delivered to memory and PC is incremented by 4. If Rst is asserted, Rst is immediately cleared, PC is cleared to zero, and T (step counter) is set to zero. This behavior is the same for all steps. In step T1, if Rst is not asserted, the memory word value is stored in the memory data register and PC is set to its incremented value. In step T2, memory data transfers to IR. In step T3, register operand values are read. In step T4, the mathematical operation executes. In step T5, the calculated value is written back to the register file. During all steps, if Rst is asserted, PC and step counter are set to zero.

💡 Why this matters: This demonstrates how reset must be handled at every clock cycle, even in the middle of multi-cycle instruction execution, ensuring the processor can be reliably brought to a known state regardless of when the reset signal arrives.

Machine Exceptions

Anything that interrupts the normal flow of execution of instructions in the processor is called an exception. Exceptions may be generated by an external or internal event such as a mouse click or an attempt to divide by zero. External exceptions or interrupts are generally asynchronous (do not depend on the system clock) while internal exceptions are synchronous (paced by internal clock). The exception process allows instruction flow to be modified in response to internal or external events or anomalies.

Exception Processing A generalized exception handler should include:

1. Logic to resolve priority conflicts — for nested exceptions, the processor must decide which has higher priority. For example, a timer interrupt might have higher priority than keyboard input.

2. Identification of interrupting device — two basic approaches exist: exception vectors (containing the address of the exception handling routine, filled by the interrupting process when acknowledged) and the “information” register (using one general purpose exception handler, saving PC and loading general purpose register address; the interrupting process fills the information register with identification data).

3. Saving the processor state — must be saved before jumping to the exception handler, including current PC value, general purpose registers, condition vector, and external flags.

4. Exception disabling during critical operation — processor must disable interrupts during context switching to prevent another exception from disrupting the transition.

Examples of Exceptions

• Reset Exception — treated as an exception by some machines (e.g., SPARC and MC68000)
• Machine Check — external exception caused by memory failure
• Data Access Exception — generated by memory management unit to protect against illegal accesses
• Instruction Access Exception — similar to data access exception
• Alignment Exception — blocks misaligned data access

Types of Exceptions

• Program Exceptions — raised during instruction decoding and execution; examples include illegal instruction (executing an instruction not in the instruction set) and privileged instruction exception.

• Hardware Exceptions — various kinds; e.g., a timer raising an exception when it counts down to zero.

• Trace and Debugging Exceptions — enabled through traps; the exception handler called after each instruction execution allows examination of program variables.

• Non-Maskable Exceptions — high priority exceptions reserved for catastrophic events such as power loss. These cannot be suppressed by the processor under any condition. In case of power loss, the processor might try to save system state to hard drive or alert an alternate power supply.

• Interrupts (External Exceptions) — exception handlers written for external interrupts, allowing programs to respond to events like keyboard or mouse events.

💡 Why this matters: Understanding the exception hierarchy and processing mechanisms is critical for designing robust systems that can handle multiple simultaneous events, recover from errors, and maintain system integrity.

⭐ Key Takeaways

The 3-bus SRC implementation uses two read buses and one write bus, requiring only two time steps for instruction fetch and one for execute in the subtract example. The machine reset operation has two types: hard reset (initializing PC, general registers, and step counter via Strt signal) and soft reset (initializing only PC via rst signal), both tested on every clock cycle. Exception processing requires mechanisms for priority resolution, device identification (via exception vectors or information registers), state saving, and interrupt disabling during critical operations. Exceptions range from program exceptions (illegal instructions) to hardware exceptions (timers), non-maskable exceptions (power loss), and external interrupts (keyboard/mouse). The reset operation itself can be implemented as an exception in some architectures like SPARC and MC68000.

🧠 Quick Revision Questions

1. What are the two essential features of a reset operation, and why is each needed?
2. How does the behavioral RTL for SRC change when adding reset capability, and what three hardware modifications are required?
3. What happens in each time step (T0 through T5) when the subtract instruction is executed with and without the Rst signal asserted?
4. List four mechanisms that a generalized exception handler must include, and explain the two approaches for identifying the interrupting device.
5. What is the difference between non-maskable exceptions and interrupts, and give an example of each.

📘 Lecture 18 — Pipelining

📖 Overview: This lecture covers the SRC exception processing mechanism, introducing how interrupts and exceptions are handled in the SRC architecture. It then introduces the fundamental concept of pipelining, explaining its stages, benefits, complications like data dependencies and branch delays, and the design requirements for implementing a pipelined processor.

🗂️ Topics Covered

The lecture begins by detailing the SRC exception processing mechanism, including the behavioral and structural RTL for interrupt handling and the additional instructions that support interrupts. It then provides a comprehensive introduction to pipelining, describing its five stages (instruction fetch, decode/operand fetch, ALU operation, memory access, register write) and the concepts of latency and throughput. The lecture concludes by discussing the complications related to pipelining such as data dependence, branch delay, and load delay, as well as the design requirements for a pipelined implementation.

📝 Lecture Summary

SRC Exception Processing Mechanism

The lecture explains how the SRC architecture handles exceptions, specifically interrupts, which are external events that require immediate processor attention. The mechanism modifies the normal instruction fetch cycle.

When an interrupt request (ireq) occurs and the interrupt enable (IE) flag is set, the processor performs the following actions:

• Saves the current PC (Program Counter) into the IPC (Interrupt PC) register.
• Loads the II (Interrupt Information) register with information from Isrc_info.
• Clears the IE flag to disable further interrupts during the handler.
• Loads the PC with the address from Ivect (Interrupt Vector), which points to the interrupt service routine.
• Sends an interrupt acknowledge signal (iack).

The lecture also introduces new instructions to support interrupts:

🔑 Definition — svi (Save Interrupt Vectors and Information): This instruction saves the contents of the II and IPC registers into general-purpose registers ra and rb, respectively. 📌 Example: svi r1, r2 → R[1]<15..0> ← II<15..0>, R[2] ← IPC

🔑 Definition — ri (Restore Interrupt Vectors and Information): This instruction restores the II and IPC registers from general-purpose registers ra and rb, respectively. 📌 Example: ri r1, r2 → II<15..0> ← R[1]<15..0>, IPC ← R[2]

🔑 Definition — een (Exception Enable): This instruction sets the IE flag to 1, enabling exception processing. 🔑 Definition — edi (Exception Disable): This instruction clears the IE flag to 0, disabling exception processing. 🔑 Definition — rfi (Return from Interrupt): This instruction restores the PC from the IPC register and re-enables interrupts by setting IE to 1, effectively returning to the interrupted program.

💡 Why this matters: This mechanism allows the processor to respond to urgent external events, save the current state, execute a special handler, and then seamlessly return to the original program.

The lecture then combines the RTL for reset and exception into a single, unified Instruction_Fetch state. It includes:

• Normal Fetch: Run & !Rst & !(ireq & IE)
• Soft Reset: Run & Rst — Clears internal state, sets IE to 0, and resets PC to 0.
• Hard Reset: !Run & Strt — Sets Run to 1, resets PC and all registers to 0.
• Interrupt: Run & !Rst & (ireq & IE) — Performs the interrupt handling sequence as described.

Introduction to Pipelining

Pipelining is a technique of overlapping the execution of multiple instructions in time. A pipelined processor issues a new instruction before the previous one completes, leading to a higher overall throughput (instructions per second). This results in more efficient use of the processor's functional units.

The lecture presents a five-stage pipeline as an example:

1. Instruction Fetch: The instruction is fetched from instruction memory and loaded into a temporary pipeline register.

2. Instruction Decode/Operand Fetch: The operands for the instruction are fetched from the register file. For example, for add r1, r2, r3, the values in r2 and r3 are read.

3. ALU Operation: The fetched operands are processed by the ALU (Arithmetic Logic Unit), also known as the ALSU (Arithmetic Logic Shift Unit). The result is stored in a temporary register. For memory access instructions (load/store), the ALU calculates the effective memory address in this stage.

4. Memory Access: For a load instruction, a memory read is performed. For a store instruction, a memory write is performed. If the instruction requires no memory access, this stage is bypassed.

5. Register Write: The result is written back to the destination register.

🔑 Definition — Latency: The time required to process a single instruction from start to finish. 🔑 Definition — Throughput: The number of instructions processed per second. 🔑 Definition — (Key Insight): Pipelining does NOT lower the latency of a single instruction, but it significantly increases the throughput of the processor. A key limitation is that the performance gain in a pipeline is limited by the slowest stage in the pipeline.

Complications Related to Pipelining

Several complications arise from overlapping instruction execution.

Data dependence occurs when an instruction in one pipeline stage uses the result of an instruction in a previous stage. For example:

S1: add r3, r2, r1
S2: sub r4, r5, r3

Here, S2 needs the value of r3 that S1 is calculating. Executing S2 before S1 completes would use an incorrect value. Two methods resolve this:

1. Pipeline Stalls: Special nop (no operation) instructions are inserted to block subsequent instructions from entering the pipeline until the dependent instruction has completed. For the example, stalls are inserted between S1 and S2.

2. Data Forwarding: Special hardware is added to the processor to transfer the result of a pipeline stage directly to another stage that needs it, without waiting for the result to be written to the register file. In the example, the result from S1's execute stage can be forwarded directly to S2's decode stage.

Branch delay is a complication where the processor cannot easily predict whether a branch will be taken before the branch condition is evaluated. If a branch is treated like a normal instruction, subsequent instructions are loaded into the pipeline. If the branch is taken, these instructions must be flushed from the pipeline and their effects undone. An alternative is to introduce stalls after the branch instruction.

Load delay is a problem that arises when a value is loaded from memory and then immediately used in the next instruction. For example:

S1: load r2, 34(r1)
S2: add r5, r2, r3

The correct value of r2 is only available after S1's memory access stage. Even with data forwarding, a stall must be placed between S1 and S2 to give the data time to arrive from memory.

Pipeline Design Requirements

For a pipelined design to work correctly, several requirements must be met:

• The program must produce the same results as on a non-pipelined machine.
• Instruction and data memories should be separate to allow instruction fetch while data is being read/written.
• There should be a single data path to maintain program execution order.
• A three-port register file is needed to read two operands and write a result in parallel.
• Data must be latched between pipeline stages using temporary registers.
• ALU operations must be quick to avoid lengthening the clock cycle for the entire pipeline.

The lecture outlines three steps for designing a pipelined implementation:

1. Adapting the instructions to pipelined execution: The instruction set must have clear, definite phases. A register-register architecture is often adopted to avoid complex instructions that mix memory and register operands, which are difficult to pipeline.

2. Designing the pipelined data path: The data path specifies the sequence of steps (like instruction fetch, register read, execute) for each instruction. It is defined in terms of registers placed between the stages and becomes more complex with forwarding mechanisms.

3. Generating control signals: Digital logic is needed to generate the control signals that regulate the flow of data through the data path.

⭐ Key Takeaways

From this lecture, a student must understand the behavioral RTL for interrupt handling in the SRC, including the role of IPC, II, IE, and the special instructions svi, ri, een, edi, and rfi. The core concept of pipelining as an overlapping technique that increases throughput without reducing latency must be grasped. The five standard pipeline stages are critical for analysis. Students must be able to identify and explain complications like data dependence (and its solutions: stalls and forwarding), branch delay, and load delay. Finally, the fundamental design requirements for a pipeline—such as separate memories, a three-port register file, and latching between stages—are essential for exam comprehension.

🧠 Quick Revision Questions

1. What are the two key events that can cause a deviation from the normal SRC instruction fetch cycle, and what are their respective behavioral RTL sequences?
2. Explain the difference between latency and throughput in the context of a pipelined processor. Does pipelining reduce latency?
3. Name the five stages of the example pipeline discussed in the lecture and describe the primary operation performed in each stage.
4. What is a data dependency? Describe the two primary methods for resolving a data dependency in a pipelined processor.
5. Why is a three-port register file a design requirement for a pipelined processor? What feature does it enable?

📘 Lecture 19 — Pipelined SRC

📖 Overview: This lecture introduces a five-stage pipelined version of the Simple RISC Computer (SRC). It explains how different categories of SRC instructions (ALU, Load/Store, and Branch) are adapted for pipelined execution and defines the control signals needed to manage the pipeline stages.

🗂️ Topics Covered

This lecture covers the five-stage pipeline structure of the SRC (Instruction Fetch, Instruction Decode/Operand Fetch, ALU Operation, Memory Access, Register Write), the adaptation of ALU, Load/Store, and Branch instructions for pipeline execution, the inter-stage pipeline registers (IR2-IR5, PC2, X3, Y3, Z4-Z5, MD3), and the control signals (alu, load, store, rl, dsp, branch, cond) used to manage multiplexers across different pipeline stages.

📝 Lecture Summary

Pipelined Version of the SRC

The SRC uses a five-stage pipeline composed of: 1) Instruction Fetch, 2) Instruction Decode/Operand Fetch, 3) ALU Operation, 4) Memory Access, and 5) Register Write. Between each stage, several pipeline registers hold intermediate values. After instruction fetch, the instruction is stored in IR2 and the incremented program counter in PC2. After register reads, the first operand goes to X3, the second to Y3, and the opcode and ra are held in IR3. For store instructions, MD3 holds the value to be stored. After ALU execution, the result is stored in Z4 and the opcode/ra in IR4. During write-back, Z5 holds the value for register storage, while opcode and ra pass to IR5.

Adapting SRC Instructions for Pipelined Execution

1. ALU Instructions ALU instructions take the form op-code ra, rb, rc or op-code ra, rb, constant. Temporary registers X3 and Y3 hold operand values between pipeline stages. X3 receives the operand value from the register file. Y3 receives either a register value or a constant from the instruction. The ALU function is determined by decoding the op-code bits. The ALU result is stored in Z4, then written to the destination register during the register write-back stage. There is no activity in the memory access stage for ALU instructions.

2. Load/Store Instructions Load/Store instructions take the form op-code ra, constant(rb). The instruction is loaded into IR2 and the incremented PC into PC2. In the next stage, X3 receives either the value from PC2 (for relative addressing) or the value from rb (for displacement addressing). Y3 receives either C1 (relative) or c2 (displacement). For store instructions, execution completes after memory access and writing to memory. For load instructions, execution completes when the loaded value is transferred back to the register file.

3. Branch Instructions Branch instructions involve calculating the target address and evaluating a condition. The condition is evaluated based on the c2 field of the IR and the value in R[rc]. If the condition is true, the PC is loaded with the value in R[rb]; otherwise, the PC is incremented by 4 as usual.

Control Signals for the Pipelined SRC

Control signals are defined by grouping similar op-codes: alu, load, store, rl (relative load), dsp (displacement), branch, and cond. In most cases, these signals are used in the same stage where they are generated. If not, a number after the signal indicates the stage of generation.

Control Signals for Different Pipeline Stages

The Mp1 signal controls the input to the PC. If branch and cond are not activated, the PC is incremented by 4. If both are activated, the value of R1 is copied into the PC.

The Mp2 multiplexer decides which registers are read from the register file. If the store signal is activated, R[rb] from the instruction bits is read (for memory storage). Otherwise, R[rc] is read.

The Mp3 multiplexer decides which registers are read for operand 1 (X3). If either rl or branch is activated, the updated value of PC2 is transferred to X3. If dsp or alu is activated, the value of R[ra] is transferred to X3.

The Mp4 multiplexer selects an input for Y3.

The MP5 multiplexer decides which value is written back to the register file. If the load signal is activated, data from memory is transferred to Z5. If load is not activated, data from Z4 (the ALU result) is transferred to Z5, which is then written back to the register file.

⭐ Key Takeaways

The SRC pipeline has five distinct stages with dedicated inter-stage registers (IR2-IR5, PC2, X3, Y3, Z4-Z5, MD3) that hold values as instructions progress. ALU instructions are the simplest, requiring no memory access stage activity. Load/Store instructions use either relative or displacement addressing modes, with X3 and Y3 receiving different inputs accordingly. Branch instructions compute the target address and evaluate the condition using R[rc] to decide whether to load a new PC value or increment by 4. The control signals (alu, load, store, rl, dsp, branch, cond) drive the multiplexers Mp1 through Mp5 to manage data flow through the pipeline, with the signal name often indicating the stage where it is generated.

🧠 Quick Revision Questions

1. What are the five stages of the SRC pipeline?
2. For a Load instruction, how are X3 and Y3 loaded differently for relative vs. displacement addressing modes?
3. What determines whether the PC is loaded with R[rb] or incremented by 4 during a Branch instruction?
4. What is the role of the Mp5 multiplexer, and what two sources can it select for writing back to the register file?
5. When a number is appended to a control signal name (e.g., signal3), what does that number indicate?

📘 Lecture 20 — Hazards in Pipelining

📖 Overview: This lecture examines the fundamental challenges that arise when executing instructions in parallel within a pipelined processor. It covers the three main categories of pipeline hazards (branch, structural, and data hazards), explains how data dependence distances affect instruction scheduling, and presents both hardware and compiler-based solutions for hazard detection and correction, including data forwarding and pipeline stalls.

🗂️ Topics Covered

The lecture provides structural RTL for all pipeline stages (fetch, decode, ALU, memory access, write back), explains instruction propagation through the pipeline with a specific code example, classifies pipeline hazards into three categories, introduces the concept of data dependence distance, discusses compiler solutions to hazards, and presents SRC hazard detection and correction mechanisms including pipeline stalls, data forwarding, and their corresponding RTL expressions.

📝 Lecture Summary

Structural RTL for Pipeline Stages

The Register Transfer Language (RTL) for each pipeline phase is defined precisely. In Instruction Fetch, the instruction is loaded from memory and the program counter is incremented: IR2 ← M[PC]; PC2 ← PC+4. During Instruction Decode & Operand Fetch, multiple operations occur simultaneously including loading operands into X3 and Y3, setting the MD3 register for store operations, and calculating the next PC value for branches. The ALU operation stage computes results in Z4 based on the instruction type (I-s, brl, or Alu). During Memory access, data is read from or written to memory based on the instruction type (load, store, branch, or ALU). Finally, in Write back, the result in Z5 is written to the register file: regwrite5: (R[ra] ← Z5).

Instruction Propagation Through the Pipeline

🔑 Pipeline Propagation: The process by which instructions move through successive pipeline stages (fetch, decode, execute, memory access, write back) each clock cycle.

📌 Example: Consider the following SRC code executing through the pipeline:

200: add r1, r2, r3
204: ld r5, [4(r7)]
208: br r6
212: str r4, 56

• Clock Cycle 1: Add enters fetch stage. PC increments from 200 to 204.
• Clock Cycle 2: Add moves to decode; operands fetched to X3 and Y3. ld enters fetch. PC becomes 208.
• Clock Cycle 3: Add executes; result written to Z4. ld decodes; displacement address calculated. br enters fetch. PC becomes 212.
• Clock Cycle 4: Add result passes through memory stage to Z5. ld executes; address calculated in Z4. br in decode; since branch is always true, PC is modified. str enters fetch. PC becomes 216.
• Clock Cycle 5: Add completes; result written to r1. ld accesses data memory; result stored in Z5. br propagates through execute. str decodes; operands fetched. Instruction at address 400 enters fetch. PC becomes 404.

💡 Why this matters: Understanding instruction propagation helps visualize how instructions overlap in time and reveals where dependencies create hazards.

Pipeline Hazards

A hazard occurs when an instruction depends on the result of a previous instruction that is not yet complete. There are three categories:

🔑 Branch Hazard: The instruction following a branch is always executed whether or not the branch is taken—this is called the branch delay slot. Compilers may insert a nop instruction in this slot. Branch delays cannot be avoided by forwarding schemes.

🔑 Structural Hazard: Occurs when attempting to access the same resource in different ways simultaneously. This happens when the hardware is insufficient to implement pipelining properly, e.g., when the machine does not support separate data and instruction memories.

🔑 Data Hazard: Occurs when an instruction attempts to access data that has not yet been updated by a previous instruction. The most common type is RAW (Read After Write) .

📌 Example of RAW data hazard:

200: add r2, r3, r4    ; writes r2 in clock cycle 5
204: sub r7, r2, r6    ; reads r2 - cannot proceed beyond stage 2 until add completes

Register r2 is written in clock cycle 5, so the sub instruction cannot proceed beyond stage 2 until the add instruction leaves the pipeline.

Data Dependence Distance

Data Dependence Distance is the minimum spacing required between two data-dependent instructions to avoid hazard. Without forwarding, this minimum distance is four. The load instruction has a minimum distance of two from all other instructions except branch. Branch delays cannot be removed even with forwarding.

Compiler Solution to Hazards

The compiler can detect hazards by analyzing instruction sequences and dependencies. It can insert bubbles (nop instructions) between two instructions that form a hazard, or it can reorder instructions to put sufficient distance between dependent instructions. However, this compiler solution is complex, expensive, and less efficient compared to hardware solutions.

SRC Hazard Detection and Correction

The SRC uses a hazard detection unit that resolves hazards using either pipeline stalls or data forwarding.

Pipeline Stalls: When using pipeline stalls, nop instructions are placed between dependent instructions. The logic: if opcode in stage 2 and 3 are both ALU, and if ra in stage 3 equals rb or rc in stage 2, then a pause signal is issued to insert a bubble between stage 3 and 2. Similar logic applies for hazards between stage 2 and 4, and stage 4 and 5.

Data Forwarding: By adding data forwarding hardware, stalls can be completely eliminated for ALU instructions. The testing and forwarding circuits employ wider IRs to store data needed in later stages. The logic: if the ALU is activated for both stages 3 and 5 and ra in stage 5 equals rb in stage 3, then Z5 (the currently loaded or calculated result) is directly forwarded to X3. Similarly, if both are ALU operations and the instruction in stage 3 does not employ immediate operands, then Z5 is transferred to Y3.

RTL for Hazard Detection and Pipeline Stall

🔑 Data hazard detection RTL for detecting hazards between stage 2 and 3:

alu3 & alu2 & ((ra3=rb2) ~ ((ra3=rc2) & !imm2)): (pause2, pause1, op3←0)

Meaning: If opcode in stage 2 and 3 are both ALU, and if ra in stage 3 is the same as rb or rc in stage 2, issue a pause signal to insert a bubble between stage 3 and 2.

Complete RTL for detecting hazards among ALU instructions:

• Stage 2 and 3: alu3 & alu2 & ((ra3=rb2) ~ ((ra3=rc2) & !imm2)): (pause2, pause1, op3←0)
• Stage 2 and 4: alu4 & alu2 & ((ra4=rb2) ~ ((ra4=rc2) & !imm2)): (pause2, pause1, op3←0)
• Stage 2 and 5: alu5 & alu2 & ((ra5=rb2) ~ ((ra5=rc2) & !imm2)): (pause2, pause1, op3←0)

⭐ Key Takeaways

Students must remember that pipeline hazards arise from instruction dependencies and are classified into three types: branch (caused by the branch delay slot), structural (caused by insufficient hardware resources), and data (caused by RAW dependencies). Data dependence distance is critical—without forwarding, the minimum spacing between dependent instructions is four, and branch delays cannot be eliminated even with forwarding. The two hardware solutions are pipeline stalls (inserting bubbles) and data forwarding (directing results from later stages back to earlier ones), with the SRC employing both through explicit RTL expressions that detect register matches between pipeline stages. The compiler solution, while possible through instruction reordering or nop insertion, is less efficient than hardware-based approaches.

🧠 Quick Revision Questions

1. What are the three categories of pipeline hazards, and what causes each type?
2. How does the instruction propagation through a 5-stage pipeline work for a sequence containing add, load, branch, and store instructions?
3. What is data dependence distance, and why is the load instruction's distance different from other instructions?
4. In the SRC hazard detection RTL, what does the expression alu3 & alu2 & ((ra3=rb2) ~ ((ra3=rc2) & !imm2)) mean in plain language?
5. How does data forwarding eliminate stalls for ALU instructions, and what are the specific forwarding paths described in the lecture?

📘 Lecture 21 — Instruction Level Parallelism

📖 Overview: This lecture explores two primary methods for increasing a processor's throughput: increasing clock speed and increasing parallel instruction execution. It introduces instruction-level parallelism (ILP) through superscalar and VLIW architectures, contrasting them with standard pipelining and detailing the hardware and design philosophies behind each approach.

🗂️ Topics Covered

The lecture begins with data forwarding hardware and its RTL representation for ALU instructions. It then introduces instruction-level parallelism and the two main approaches to achieve it: superscalar architecture and VLIW architecture. The differences between pipelining and instruction-level parallelism are outlined, followed by detailed explanations of superscalar architecture, superscalar design, and VLIW architecture, including examples of superscalar processors.

📝 Lecture Summary

Data Forwarding Hardware

The concept of data forwarding was introduced in the previous lecture. This hardware resolves data hazards by forwarding results from a later pipeline stage directly to an earlier stage that needs the data, rather than waiting for the write-back stage. The lecture provides RTL (Register Transfer Language) for data forwarding specifically for ALU instructions.

🔑 Definition — Data Forwarding: A hardware technique that resolves data hazards by passing the result of an instruction from a later pipeline stage directly to an earlier stage that requires it as an operand, bypassing the register file.

📐 Formula: Dependence RTL for Stage 3-5: alu5&alu3:((ra5=rb3):X←Z5, (ra5=rc3)&!imm3: Y ← Z5); → This means when the ALU stage 5 result is ready and stage 3 needs a register, if the register address from stage 5 (ra5) matches the B register address from stage 3 (rb3), forward the Z5 result to the X input. Similarly, if ra5 matches rc3 and the instruction is not immediate, forward Z5 to the Y input.

📌 Example: For Stage 3-4 forwarding: alu4&alu3:((ra4=rb3):X←Z4, (ra4=rc3)&!imm3: Y ← Z4); — This checks if instructions in ALU stage 4 and stage 3 have a register dependency. If the destination register of the instruction in stage 4 (ra4) equals the source register of the instruction in stage 3 (rb3), the result from stage 4 (Z4) is forwarded to the ALU input X of stage 3.

Instruction-Level Parallelism

Instruction-Level Parallelism (ILP) refers to the degree to which the instructions of a program can be executed in parallel. There are two ways to increase the number of instructions executed in a given time by a processor: by increasing the clock speed, and by increasing the number of instructions that can execute in parallel.

Increasing the clock speed is an IC design issue and depends on advancements in chip technology, which the computer architect or logic designer cannot manipulate. However, the architect can increase the number of instructions processed per unit time. In pipelining, instructions are executed in a staggered fashion. Taking this concept further, multiple data paths allow multiple pipelines to execute simultaneously. The two main categories of these parallel instruction processors are superscalar and VLIW (Very Long Instruction Word).

🔑 Definition — Superscalar Architecture: A scalar processor that can issue multiple instructions simultaneously is said to be superscalar.

🔑 Definition — VLIW Architecture: A VLIW processor is based on a very long instruction word. VLIW relies on instruction scheduling by the compiler, which forms instruction packets that can run in parallel without dependencies.

Difference between Pipelining and Instruction-Level Parallelism

Superscalar Architecture

A superscalar machine has one or more IUs (Integer Units), FPUs (Floating Point Units), and BPUs (Branch Prediction Units). It divides instructions into three classes: Integer, Floating point, and Branch prediction. The general operation involves fetching multiple instructions, decoding some of their portion to determine the class, and dispatching them to the corresponding functional unit. The superscalar design uses multiple pipelines to implement instruction level parallelism.

The Branch Prediction Unit (BPU) calculates the branch target address ahead of time to save CPU cycles. Branch instructions are routed from the queue to the BPU where the target address is calculated and supplied when required without any stalls. The BPU also starts executing branch instructions by speculating and discards the results if the prediction turns out to be wrong.

Superscalar Design

The philosophy behind a superscalar design is to prefetch and decode as many instructions as possible before execution, start several branch instruction streams speculatively on the basis of this decoding, and finally discard all but the correct stream of execution. This architecture uses multiple instruction issues and techniques such as branch prediction and speculative instruction execution, where it speculates on whether a particular branch will be taken and then continues to execute it and the following instructions. The results are not written back to the registers until the branch decision is confirmed. Most superscalar architectures contain a reorder buffer, which acts like an intermediary between the processor and the register file. All results are written onto the reorder buffer, and when the speculated course of action is confirmed, the reorder buffer is committed to the register file.

💡 Why this matters: The reorder buffer is a critical hardware structure that allows superscalar processors to execute instructions out-of-order (for efficiency) while still committing their results in the original program order, ensuring correct program execution despite speculative execution.

Examples of superscalar processors include the PowerPC 601, Intel P6, and DEC Alpha 21164.

VLIW Architecture

VLIW stands for "Very Long Instruction Word," typically 64 or 128 bits wide. The longer instruction word carries information to route data to register files and execution units. The execution-order decisions are made at compile time, unlike the superscalar design where decisions are made at run time. Branch instructions are not handled very efficiently in this architecture. The VLIW compiler makes use of techniques such as loop unrolling and code reordering to minimize dependencies and the occurrence of branch instructions.

⭐ Key Takeaways

Instruction-level parallelism is the ability to execute multiple instructions simultaneously, distinct from pipelining which overlaps sequential instruction stages. Two primary architectural approaches achieve ILP: superscalar (hardware-intensive, run-time decision making) and VLIW (compiler-intensive, compile-time decision making). Superscalar processors rely on complex hardware like reorder buffers for speculative execution and branch prediction units to manage branch hazards, whereas VLIW architectures shift the complexity to the compiler for static scheduling. Understanding the trade-off between hardware and compiler involvement is central to modern processor design.

🧠 Quick Revision Questions

1. What are the two main ways to increase a processor's throughput?
2. How does instruction-level parallelism differ from standard pipelining?
3. What is the key difference between how a superscalar and a VLIW processor handle instruction scheduling?
4. What is the role of a reorder buffer in a superscalar processor?
5. Why does the VLIW architecture rely heavily on the compiler?

📘 Lecture 22 — Microprogramming

📖 Overview: This lecture introduces microprogramming as an alternative method for designing the control unit in a computer processor. It explains the structure and working of a microcoded controller, compares it with hardwired control, and covers concepts like microprogram memory, horizontal and vertical microcode schemes, and the microcoded 1-bus SRC design.

🗂️ Topics Covered

The lecture covers the concept of microprogramming and microcoded control units, the working of a general microcoded controller including its components like micro-PC and microprogram memory, and the generation of microcode for sample instructions. It also discusses the layout of microprogram memory, branching and looping in microcode, and compares horizontal and vertical microcode schemes. Finally, it presents the microcoded 1-bus SRC design and the SRC microprogram controller.

📝 Lecture Summary

Microprogramming

Microprogramming (or microcoding) is an alternative way to design the control unit. In a microprogrammed control unit, all the control signals needed at a certain time are stored together in a control word, which is called a microinstruction. A collection of microinstructions is called a microprogram. These microprograms generate the sequence of necessary control signals required to process an instruction and are stored in a memory called the control store. The microcoded control unit is itself a small stored program computer consisting of a Micro-PC, a Microprogram memory, and a Microinstruction word.

Working of a general microcoded controller

A microcoded controller works like a small general-purpose computer. Its operation is a cycle of three steps:

1. Fetch a micro-instruction and increment the micro-PC.
2. Execute the instruction present in the micro-IR (Micro-Instruction Register).
3. Fetch the next instruction and so on.

The micro-PC is controlled by the microprogram controller. The value of the micro-PC depends on a 4-to-1 MUX. The source may be the incremented micro-PC value, a calculated branch value, or a value derived by decoding an opcode for an instruction. The microprogram memory writes the control word at the chosen address into the microinstruction register.

Fields in the micro instruction A control word has three main fields:

• C Bits: These form the control signal field.
• M Bits: These form the branch address field.
• B Bits: These form the branch control field.

Loading the micro-PC The micro-PC can be loaded from one of four possible sources:

• Simple increment: Steps sequentially from microinstruction to microinstruction.
• Lookup table: A lookup table maps the opcode field to the starting address of the microcode routine that generates control signals.
• External source: Initializes micro-PC to begin an operation, e.g., interrupt service, reset.
• Branch addresses: Jumps anywhere in the microprogram memory on the basis of conditional or unconditional branch.

Microprogram Memory

This is a small, fast memory that contains micro routines for all the instructions in the ISA. The micro-PC supplies the address, and the microprogram memory returns the control word stored at that address. It is much faster and smaller than a typical main memory.

Generating Microcode for Some Sample Instructions

The control word for an instruction is used to generate the equivalent microcode sequence. Each step in RTL (Register Transfer Language) corresponds to a microinstruction executed to generate the control signals. Each bit in the control words in the microprogram memory represents a control signal, and its value (0 or 1) decides whether the signal is to be activated.

🔑 Definition — RTL: A register transfer language is used to describe the sequence of micro-operations (register transfers) that occur in a computer system.

Example: Control Signals for the sub Instruction For the SRC processor, the first three addresses (e.g., 100 to 102) represent microcode for instruction fetch. The last three addresses (e.g., 203 to 205) represent microcode for the sub instruction.

• At address 100, the control signals PCout, LMAR, LC, and INC4 are activated. This corresponds to the structural RTL description of the T0 clock during the instruction fetch phase.
• The content of address 101 corresponds to T1, and the content of address 102 corresponds to T2.

Microprogram Controller functions: Branching and looping The microprogram controller controls the sequence of the flow of microinstructions. Its inputs are from the branch control fields specified in the microcode word. Its output controls the 4-to-1 multiplexer inside the microcoded control unit. It implements conditional execution and both conditional and unconditional branches. If a branch instruction is encountered within the microprogram, hardwired logic selects the branch address as the source of the micro-PC using the 4-to-1 MUX.

4-1 Multiplexer The multiplexer supplies one of four possible values to the micro-PC:

1. The incremented value of the micro-PC (used for the normal sequential flow).
2. The opcode from the instruction (used to set the micro-PC when a microroutine is initially loaded).
3. An external address (used to reset the microprogram controller).
4. A branch address (set when a branch microinstruction is encountered).

How to form a branch A branch can be implemented by choosing one alternative from a list of conditions and one from a list of address sources. This scheme provides flexibility, as any combination of conditions and addresses can be formed.

📐 Formula: Branch Condition → Next Address

• Condition: Unconditional, Branch if Zero, Branch if Negative, Branch if Overflow.
• Address: Opcode, Next Sequential, Branch Address from Microinstruction.

Similarity between microcode and high level programs Any high-level construct, such as if-else, while, or repeat, can be implemented using microcode. A variety of microcode compilers are available that allow easier programming in microcode. This similarity simplifies the task of controller design.

Horizontal and vertical microcode schemes

In horizontal microcode schemes, there are no intermediate decoders. The control word bits are directly connected to their destination. Each bit in the control word is directly connected to some control signal, and the total number of bits in the control word equals the total number of control signals in the CPU.

Vertical microcode schemes employ an extra level of decoding to reduce the control word width. From an n-bit control word, we may have 2^n bit signal values. However, a completely vertical scheme is not feasible because of the high degree of fan-out.

💡 Why this matters: Horizontal microcode is very fast but requires a wide control word, while vertical microcode reduces the width at the cost of speed due to the extra decoding delay.

Microcoded 1-bus SRC design

In the SRC (Simple RISC Computer), the bits from the opcode in the instruction register are decoded to fetch the address of the suitable microroutine from the microprogram memory. The microprogram controller for the SRC microcoded control unit employs the logic for handling exceptions and the reset process. Since the SRC does not have any condition codes, it uses the CON and n signals instead of the N and Z flags to control branches for instructions like "branch if equal to zero" or "branch if less than".

Microcode for some SRC instructions Assume the first control word for an instruction fetch is at address 300. The RTL for this step is MAR <- PC; C <- PC+4. To facilitate these actions, the PCout signal bit and the LMAR signal bit are set to one, so the value of the PC may be written to the internal processor bus and written onto the MAR. The instructions at addresses 300, 301, and 302 form the microcode for the instruction fetch. In this sequence, the value of PC is incremented, the old value of PC is sent to memory, and the instruction from that address is loaded into the MBR (Memory Buffer Register). Then, the opcode of the fetched instruction is used to invoke the appropriate microroutine.

🔑 Definition — CON and n signals: Control signals used in the SRC microcontroller to handle conditional branches, replacing traditional N and Z condition code flags.

Alternative approaches to microcoding Several other approaches exist in microcoding:

• Bit ORing
• Nanocoding
• Writable Microprogram Memory
• Subroutines in Microprogramming

⭐ Key Takeaways

The most critical concepts from this lecture are that microprogramming implements the control unit as a small stored-program computer using a control store of microinstructions, with each microinstruction generating control signals for one clock cycle. The micro-PC sequencing is managed by a 4-to-1 multiplexer with options for incremental, opcode-based, external, or branch address loading. Horizontal microcode is wide and fast with no decoding, while vertical microcode is narrower and slower due to extra decoding. The SRC processor uses a microcoded controller with the CON signal for branching instead of condition code flags, and the instruction fetch phase is a multi-step microcode routine that loads the MBR and invokes the correct microroutine.

🧠 Quick Revision Questions

1. What are the three main components of a microcoded control unit?
2. What are the three fields (C, M, B bits) in a microinstruction word, and what is the purpose of each?
3. How does the 4-to-1 multiplexer in the microcoded controller select the next value for the micro-PC?
4. What is the key difference between horizontal and vertical microcode schemes in terms of control word structure and decoding?
5. In the SRC microprogrammed controller, why are the CON and n signals used instead of N and Z flags?