VU Final Term Past Papers
136 solved final term past paper MCQs for CS302 (Digital Logic Design) at Virtual University, each with the correct answer marked. Use them to learn the VU question style and test your recall. An independent study tool — not affiliated with VU.
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Q1. Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer.
Q2. ____________ is said to occur when multiple internal variables change due to change in one input variable.
Q3. The latch is said to be in logic _________ state when Q=1 and Q'=0, and it is in the logic low state when Q=0 and Q'=1.
Q4. Asynchronous means that ___________.
Q5. A _________ can not operate without a memory element.
Q6. __________ flip-flops are obsolete now.
Q7. __________ occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
Q8. An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________Q output of all flip-flops to the clock input of the next flip-flops.
Q9. GAL can be reprogrammed as instead of fuses, E2CMOS logic is used which can be programmed to connect a _________ with a _________.
Q10. Three cascaded modulus-10 counters have an overall modulus of ________.
Q11. The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
Q12. 74HC163 has two enable input pins which are _______ and _________
Q13. The _____________ input overrides the ________ input
Q14. A decade counter is __________.
Q15. In asynchronous transmission when the transmission line is idle, _________
Q16. A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
Q17. In a sequential circuit the next state is determined by ________ and _______
Q18. The divide-by-60 counter in digital clock is implemented by using two cascading counters:
Q19. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
Q20. A Nibble consists of _____ bits
Q21. Excess-8 code assigns _______ to “-8”
Q22. The voltage gain of the Inverting Amplifier is given by the relation ________
Q23. LUT is acronym for _________
Q24. The three fundamental gates are ___________
Q25. The total amount of memory that is supported by any digital system depends upon ______
Q26. Stack is an acronym for _________
Q27. ___________ is one of the examples of synchronous inputs.
Q28. In a state diagram, the transition from a current state to the next state is determined by
Q29. ________ is used to simplify the circuit that determines the next state.
Q30. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
Q31. The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
Q32. A multiplexer with a register circuit converts _________
Q33. GAL is essentially a ________.
Q34. In order to synchronize two devices that consume and produce data at different rates, we can use _________
Q35. A flip-flop changes its state when ________________
Q36. A frequency counter ______________
Q37. Flip flops are also called _____________
Q38. Given the state diagram of an up/down counter, we can find ________
Q39. The output of this circuit is always ________.
Q40. The diagram given below represents __________
Q41. DRAM stands for __________
Q42. The expression F=A+B+C describes the operation of three bits _____ Gate.
Q43. The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary numbers.
Q44. The basic building block for a logical circuit is _______
Q45. The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.
Q46. ___________ is one of the examples of asynchronous inputs. ► J-K input
Q47. ________ is used to minimize the possible no. of states of a circuit.
Q48. The best state assignment tends to ___________.
Q49. 5-bit Johnson counter sequences through ____ states
Q50. The address from which the data is read, is provided by _______
Q51. FIFO is an acronym for __________
Q52. ______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output.
Q53. Above is the circuit diagram of _______.
Q54. The sequence of states that are implemented by a n-bit Johnson counter is
Q55. An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______
Q56. DE multiplexer is also called
Q57. A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
Q58. ____________ Counters as the name indicates are not triggered simultaneously.
Q59. A synchronous decade counter will have _______ flip-flops
Q60. The alternate solution for a demultiplexer-register combination circuit is _________
Q61. The 4-bit 2‟s complement representation of “+5” is _____________
Q62. The storage cell in SRAM is
Q63. What is the difference between a D latch and a D flip-flop?
Q64. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will______ if the clock goes HIGH.
Q65. The OR gate performs Boolean ___________.
Q66. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be
Q67. The power dissipation, PD, of a logic gate is the product of the
Q68. A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.
Q69. NOR Gate can be used to perform the operation of AND, OR and NOT Gate
Q70. Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer
Q71. The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
Q72. In designing any counter the transition from a current state to the next sate is determined by
Q73. Sum term (Max term) is implemented using ________ gates
Q74. If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop
Q75. If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
Q76. We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________
Q77. A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.
Q78. In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip- flop of the shift register.
Q79. The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines
Q80. Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state
Q81. A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1?
Q82. THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
Q83. The design and implementation of synchronous counters start from _________
Q84. THE HOURS COUNTER IS IMPLEMENTED USING __________
Q85. The high density FLASH memory cell is implemented using ______________
Q86. Q2 :=Q1 OR X OR Q3 The above ABEL expression will be
Q87. Generally, the Power dissipation of _______ devices remains constant throughout their operation.
Q88. When the control line in tri-state buffer is high the buffer operates like a ________gate
Q89. 3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series.
Q90. The output of an AND gate is one when _______
Q91. The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
Q92. The diagram above shows the general implementation of _____ form
Q93. The device shown here is most likely a
Q94. DE multiplexer converts _______ data to __________ data
Q95. In asynchronous digital systems all the circuits change their state with respect to a common clock
Q96. Which is not characteristic of a shift register?
Q97. The output of an XNOR gate is 1 when ____________ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one
Q98. NAND gate is formed by connecting _________
Q99. Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____
Q100. The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called __________
Q101. Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.
Q102. In ________ outputs depend only on the combination of current state and inputs.
Q103. In the following statement Z PIN 20 ISTYPE „reg.invert‟; The keyword “reg.invert” indicates ________
Q104. The process of converting the analogue signal into a digital representation (code) is known as ___________
Q105. ( A B )( A B C )( A C ) is an example of ______________
Q106. Caveman number system is Base ______ number system ► 2
Q107. The output of an XOR gate is zero (0) when __________ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one
Q108. The simplest and most commonly used Decoders are the ______ Decoders
Q109. The _______ Encoder is used as a keypad encoder.
Q110. 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
Q111. If the S and R inputs of the gated S-R latch are connected together using a ______gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
Q112. The low to high or high to low transition of the clock is considered to be a(n) ________
Q113. RCO Stands for _________
Q114. A transparent mode means _____________
Q115. In ________ outputs depend only on the current state.
Q116. Smallest unit of binary data is a ________
Q117. NOR gate is formed by connecting _________
Q118. THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE
Q119. A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER.
Q120. The alternate solution for a multiplexer and a register circuit is _________
Showing the first 120 of 136 MCQs.