CS302 — Final Term Summary (Lectures 23–45)

📘 Lecture 23 — Application of S-R Latch

📖 Overview: This lecture explores the practical application of S-R latches in digital systems, particularly for switch debouncing and alarm circuits. It then progresses to gated latches and edge-triggered flip-flops, which are fundamental building blocks for synchronous digital systems. Understanding these components is crucial for designing reliable sequential logic circuits that operate in synchronization with a clock signal.

🗂️ Topics Covered

The lecture begins with the application of S-R latches for switch debouncing and alarm circuits, followed by the introduction of gated S-R and D latches with enable inputs. It then covers edge-triggered S-R, D, and J-K flip-flops, their operation and timing diagrams, and asynchronous preset/clear inputs. Finally, it discusses master-slave flip-flops and important flip-flop operating characteristics including propagation delays, setup and hold times, and power dissipation.

📝 Lecture Summary

Application of S-R Latch

Digital systems use switches for input, but when a switch closes, its contacts physically 'bounce' before making solid contact. This switch bounce causes the output voltage to vary between logic low and high briefly before settling. An S-R latch connected between the switch and the digital circuit prevents this varying output from causing erratic circuit behavior. When the switch is moved, the S input may vary due to bounce, but the latch doesn't change its output state when S=1 and R=1.

A burglar alarm circuit uses an S-R latch where an alarm switch connects the S input to logic high. The alarm is activated by setting the reset switch to ground. When an intruder opens a door, the alarm switch grounds the set input, setting Q to logic 1 and activating the alarm. Even if the door is closed, the alarm continues to sound as S=1 and R=1 maintain the output. The alarm can only be disabled by reconnecting the reset switch to ground.

The S-R NAND gate based latch is available as the 74LS279 IC, which contains four independent S-R latches.

The Gated S-R Latch

The gated S-R latch has an enable input that must be activated to operate the latch. In this circuit, the S and R inputs are applied to NAND gates 1 and 2 only when the enable input is active-high. When the enable input is logic low, the outputs of NAND gates 3 and 4 remain logic 1 regardless of S and R, keeping Q and Q̅ in their previous state.

🔑 Definition — Gated S-R Latch: A sequential logic circuit where the S and R inputs only affect the output when an enable signal is active. 📐 Truth Table: When EN=0, output remains Qₜ regardless of inputs. When EN=1 and S=0, R=0, output remains Qₜ. When S=0, R=1, output is 0. When S=1, R=0, output is 1. When S=1, R=1, the state is invalid. 💡 Why this matters: The enable input provides control over when the latch can change state, which is essential for synchronizing operations in digital systems.

The Gated D Latch

The gated D-latch is created by connecting the S and R inputs of a gated S-R latch together using a NOT gate, resulting in a single input D. This reduces the four input combinations of the S-R latch to only two: D=0 or D=1. The Q output of the D latch follows the D input when enabled.

🔑 Definition — Gated D Latch: A gated latch with a single data input D that simplifies the input requirements of an S-R latch. 📐 Truth Table: When EN=0, output remains Qₜ. When EN=1 and D=0, output is 0. When EN=1 and D=1, output is 1.

Application of Gated D Latch

The D latch is available as the 74LS75 IC, which contains four independent D latches. Gated D latches can store binary information. A circuit using gated D-latches connected at the input of a 1-of-8 multiplexer can store a byte value (parallel data). The multiplexer then accesses each bit value stored in the D-latch and routes it to the output, converting 8-bit parallel data into serial data.

Edge-Triggered Flip-Flop

Flip-flops are synchronous bi-stable devices (bi-stable multivibrators) that have a clock input instead of a simple enable input. The output can only change when appropriate inputs are applied at S and R and a clock signal is applied. In synchronous systems, all digital circuit outputs change when a clock signal is applied, either at the low-to-high (positive edge) or high-to-low (negative edge) transition of the clock. Three types of edge-triggered flip-flops are commonly used: S-R, D, and J-K flip-flops.

🔑 Definition — Edge Detection Circuit: A simple combinational circuit that allows a flip-flop to change state on either the positive or negative transition of the clock signal.

Edge-Triggered S-R Flip-flop

The edge-triggered S-R flip-flop changes state only at the clock edge. A positive edge-triggered flip-flop changes on low-to-high transition, while a negative edge-triggered one changes on high-to-low transition.

🔑 Definition — Positive/Negative Edge-Triggered S-R Flip-flop: A flip-flop that samples S and R inputs only at the rising or falling edge of the clock signal. 📐 Truth Table (Positive Edge): When CLK=0 or 1 (no edge), output remains Qₜ. On rising edge (↑), if S=0, R=0, output is Qₜ; if S=0, R=1, output is 0; if S=1, R=0, output is 1; if S=1, R=1, output is invalid.

Edge-Triggered D Flip-flop

The edge-triggered D flip-flop has a single data input D. The output of the D flip-flop follows the D input at the clock edge.

🔑 Definition — Edge-Triggered D Flip-flop: A flip-flop that captures the value of the D input only at the active clock edge. 📐 Truth Table (Positive Edge): On rising edge (↑), if D=0, output is 0; if D=1, output is 1. Output remains Qₜ when no clock edge occurs.

Edge-Triggered J-K Flip-flop

The J-K flip-flop is widely used in digital circuits. Its operation is similar to the S-R flip-flop except it has no invalid state; instead, it toggles its state when both inputs are 1. When J=0 and K=0, the previous state is maintained. When J=0 and K=1, the flip-flop is reset (Q=0, Q̅=1). When J=1 and K=0, the flip-flop is set (Q=1, Q̅=0). When J=1 and K=1, the output toggles from the previous state.

🔑 Definition — J-K Flip-flop: An edge-triggered flip-flop that can set, reset, hold, or toggle its output based on the J and K inputs. 📐 Truth Table (Positive Edge): On rising edge (↑), if J=0, K=0, output is Qₜ; if J=0, K=1, output is 0; if J=1, K=0, output is 1; if J=1, K=1, output is Q̅ₜ (toggles).

Asynchronous Preset and Clear Inputs

Preset (PRE) and Clear (CLR) are asynchronous inputs that set or reset the flip-flop to a known logic level independently of the clock signal. They override the synchronous inputs. To preset the flip-flop (Q=1, Q̅=0), PRE is set to 0. To clear the flip-flop (Q=0, Q̅=1), CLR is set to 0. Setting both PRE and CLR to 0 is not allowed. To use the flip-flop in synchronous mode, both PRE and CLR are set to logic 1.

The 74HC74 is a dual positive-edge triggered D flip-flop with asynchronous inputs. The 74HC112 is a dual positive-edge triggered J-K flip-flop with asynchronous inputs.

Master-Slave Flip-Flops

Master-Slave flip-flops have become obsolete and are being replaced by edge-triggered flip-flops. They consist of two stages: the Master and the Slave, both gated S-R flip-flops. The master-slave flip-flop is a pulse triggered flip-flop as it operates on both positive and negative clock cycles. Inputs are applied during the first half of the clock signal (Master enabled), and outputs change during the second half (Slave enabled).

Flip-Flop Operating Characteristics

Several operating characteristics specify flip-flop performance:

• Propagation Delay: The interval between input application and output change. Four types are measured: tPLH from clock to low-to-high output, tPHL from clock to high-to-low output, tPLH from preset to low-to-high output, and tPHL from clear to high-to-low output. All are measured at 50% transition marks.
• Set-up Time: The minimum time input logic levels must remain stable before the clock transition.
• Hold Time: The minimum time the input signal must be maintained after the clock transition.
• Maximum Clock Frequency (fmax): The highest rate at which the flip-flop operates reliably.
• Pulse Width: The minimum specified duration for clock, preset, and clear signals for correct operation. The clock signal has specified minimum high and low times.
• Power Dissipation: Defined as P = Vcc × Icc. For example, a flip-flop connected to +5V drawing 5mA dissipates 25mW.

💡 Why this matters: These operating characteristics are critical for designing reliable digital circuits, ensuring proper timing relationships between signals, and selecting appropriate power supplies.

⭐ Key Takeaways

S-R latches are essential for eliminating switch bounce in digital input circuits and for creating alarm systems with persistent state. Gated latches introduce an enable input that controls when the latch can change state, while edge-triggered flip-flops use a clock signal for precise synchronization in digital systems. The J-K flip-flop is the most versatile as it can hold, set, reset, or toggle its output without an invalid state. Asynchronous preset and clear inputs override clocked operation to initialize flip-flops to known states, and understanding flip-flop operating characteristics like propagation delay, setup time, and hold time is essential for reliable circuit design.

🧠 Quick Revision Questions

1. How does an S-R latch eliminate the effect of switch bounce in a digital input circuit?
2. What is the difference between a gated S-R latch and an edge-triggered S-R flip-flop?
3. Why does the J-K flip-flop have no invalid state, and what happens when both J and K inputs are logic 1?
4. What is the purpose of asynchronous Preset and Clear inputs, and why can't they both be set to 0?
5. What are the four types of propagation delays measured in flip-flops, and at what percentage of signal transition are they measured?

📘 Lecture 24 — APPLICATIONS OF EDGE-TRIGGERED D FLIP-FLOP

📖 Overview: This lecture explores real-world applications of edge-triggered D flip-flops, including data storage, synchronizing asynchronous signals, and parallel data transfer. It then introduces the edge-triggered J-K flip-flop, detailing its operation, truth tables, and key applications such as sequence detection, frequency division, shift registers, and counters. Understanding these applications is crucial for designing stable and synchronized digital systems.

🗂️ Topics Covered

The lecture begins with applications of the edge-triggered D flip-flop, specifically its use in parallel data storage for multiplexer-based converters and in synchronizing asynchronous inputs to prevent partial clock pulses. It covers parallel data transfer using multi-bit registers. The latter half introduces the edge-triggered J-K flip-flop, explaining its four input combinations and operation. The lecture concludes with J-K flip-flop applications as a sequence detector, frequency divider, shift register, and counter.

📝 Lecture Summary

1. Data Storage using D-flip-flop

A Multiplexer based Parallel-to-Serial converter requires stable parallel data at its inputs during conversion. D-latches can be used, but they have a transparent mode when enabled, where data changes at the input directly appear at the output. This can be problematic if input data changes during the enable window. A better solution uses edge-triggered D flip-flops, which store data precisely at the clock transition (e.g., rising edge). Once stored, any subsequent changes to the input data have no effect on the output until the next clock edge.

🔑 Definition — Transparent Mode: A state of a D-latch where changes in the input data are directly reflected at the output as long as the enable signal is active. 🔑 Definition — Latched Mode: A state of a D-latch where changes in the input data are not reflected at the output; the output holds its last stored value. 💡 Why this matters: Edge-triggered D flip-flops provide precise and stable data storage, essential for reliable parallel-to-serial conversion and other memory applications.

📌 Example: A timing diagram in the lecture (Fig. 24.2) shows a scenario with 4 D inputs (D0, D1, D2, D3) that are constantly changing. At interval t1, a clear input resets all four D flip-flops' outputs (Q0, Q1, Q2, Q3) to 0. At interval t2, on the rising edge of the clock, the current data at D0-D3 is latched. The outputs then remain stable despite further changes at the inputs.

2. Synchronizing Asynchronous inputs using D flip-flop

In synchronized digital systems, all circuits change state with a common clock. External inputs from switches or keypads are asynchronous and can occur at any time. If an asynchronous input is directly fed into a circuit like an AND gate along with a clock signal, it can cause incomplete or partial pulses at the output, leading to system errors. A D flip-flop is used to synchronize this input. The asynchronous signal is connected to the D input, and the clock is applied to the flip-flop's clock input. The flip-flop's Q output, which only changes on the clock edge, now provides a clean, synchronized version of the input, ensuring complete clock pulses at the AND gate's output.

🔑 Definition — Asynchronous Input: An input signal that is not synchronized with the system's master clock and can change at any arbitrary time. 🔑 Definition — Synchronization: The process of aligning an asynchronous signal with a system's clock using a flip-flop so that it changes state only at clock edges.

📌 Example: In Fig 24.3 and 24.4, a switch provides an asynchronous input to a 2-input AND gate, with the other input being the clock. The resulting output (Fig 24.4) shows partial or "glitchy" pulses. By placing a D flip-flop between the switch and the AND gate (Fig 24.5), the D flip-flop's Q output now provides a clean, synchronized signal that aligns with the clock, producing complete, full-width clock pulses at the AND gate's output (Fig 24.6).

3. Parallel Data Transfer using D flip-flop

Microprocessors use registers, which are groups of multi-bit flip-flops, to store information, such as data from an ALU. A register is a set of edge-triggered D flip-flops connected in parallel. The clock inputs of all flip-flops in the register are connected together, allowing for the simultaneous latching of a multi-bit data word (e.g., an 8-bit byte) on a single clock edge.

🔑 Definition — Register: A digital circuit composed of multiple flip-flops (typically D flip-flops) connected in parallel to store a multi-bit binary word.

Edge-Triggered J-K Flip-flop

The J-K flip-flop is a versatile and widely used flip-flop. It is similar to the S-R flip-flop but has no invalid state. Instead, the J=1, K=1 condition causes the output to toggle (change to the opposite state). Its circuit has feedback where the Q and Q' outputs are connected back to the input NAND gates. Its operation for the four input combinations is:

1. J=0, K=0: The previous state is maintained; no change.
2. J=0, K=1: The flip-flop is reset, setting Q=0 and Q'=1.
3. J=1, K=0: The flip-flop is set, setting Q=1 and Q'=0.
4. J=1, K=1: The output toggles. If Q=1, Q'=0, it becomes Q=0, Q'=1, and vice versa.

🔑 Definition — Toggle: A state change in a flip-flop where the output transitions from its current state (0 or 1) to the opposite state (1 or 0).

📐 Formula: For a positive edge-triggered J-K flip-flop, the next state (Qt+1) is:

• Qt+1 = Qt (if J=0, K=0)
• Qt+1 = 0 (if J=0, K=1)
• Qt+1 = 1 (if J=1, K=0)
• Qt+1 = Qt' (if J=1, K=1)

Table 24.1 (from lecture) provides the full truth tables for positive and negative edge-triggered J-K flip-flops.

Applications of Edge-Triggered J-K Flip-flop

1. J-K flip-flop used as sequence detector: By connecting inputs J and K to specific signals, a J-K flip-flop can be configured to recognize a particular sequence of inputs and change its state or activate an output only when that sequence occurs.

2. J-K flip-flop used as frequency divider: A single J-K flip-flop with its J and K inputs tied to logic 1 (high) will toggle its output on every clock edge. This produces an output signal with a frequency exactly half of the clock input frequency. 📌 Example: A 4MHz clock signal is applied to the first flip-flop (F0). Its output (Q0) is a 2MHz signal. This 2MHz signal is then used as the clock for a second flip-flop (F1). The output of the second flip-flop (Q1) is a 1MHz signal. This is a divide-by-4 frequency divider.

3. J-K flip-flop used as a shift register: J-K flip-flops can be connected in series to form a shift register, where the output of one flip-flop is connected to the input (J, K) of the next. On each clock pulse, the data bits shift one position to the right or left (Fig 24.14). This hardware efficiently performs multiplication or division by powers of 2.

4. J-K flip-flop used as a counter: J-K flip-flops are the fundamental building blocks of counters. By connecting the Q output of one flip-flop to the clock input of the next (ripple counter) and configuring their J and K inputs, a circuit can count up or down through a sequence of binary numbers with each clock pulse. 📌 Example: A 2-bit up-counter (Fig 24.15) uses two J-K flip-flops. The first F0 toggles on every clock pulse. The second F1 toggles only when F0's output is 1. The outputs (F1, F0) produce the binary sequence 00, 01, 10, 11 for four clock cycles.

⭐ Key Takeaways

The most critical concepts are the distinction between the transparent mode of a latch and the edge-triggered storage of a D flip-flop, and the latter's crucial role in synchronizing asynchronous inputs for reliable digital circuit operation. You must master the complete truth table and operation of the J-K flip-flop, especially its toggle mode with J=K=1. The ability to explain how a J-K flip-flop functions as a frequency divider (by connecting J and K to 1) and as a building block for counters and shift registers is essential for exam problems and system design.

🧠 Quick Revision Questions

1. What is the fundamental difference between a gated D-latch and an edge-triggered D flip-flop in terms of when they sample their input?
2. Explain why an asynchronous input from a switch can cause a problem when combined with a clock signal in an AND gate, and how a D flip-flop solves this problem.
3. What is the state of the Q output of a positive edge-triggered J-K flip-flop if the clock transitions from 0 to 1, J=1, and K=0? What if J=1 and K=1?
4. If a 16 MHz clock signal is applied to a divide-by-2 frequency divider, what is the frequency of the output signal? If that output is then connected to another identical frequency divider, what is the resulting frequency?
5. Describe the difference between a register (parallel data transfer) and a shift register. How is a shift register typically used to perform a multiplication by 2?

📘 Lecture 25 — ASYNCHRONOUS PRESET AND CLEAR INPUTS

📖 Overview: This lecture covers asynchronous Preset and Clear inputs in flip-flops, which override synchronous inputs to force the flip-flop into a known initial state independently of the clock. It also explores Master-Slave flip-flops, key flip-flop operating characteristics, and one-shot monostable multivibrators, explaining their circuit behavior, timing, and practical applications in digital design.

🗂️ Topics Covered

The lecture begins by explaining asynchronous Preset and Clear inputs for J-K and D flip-flops, including circuit diagrams, truth tables, and timing diagrams. It then discusses Master-Slave flip-flop architecture and operation with a pulse-triggered clock. Next, it details six key flip-flop operating characteristics: propagation delay, set-up time, hold time, maximum clock frequency, pulse width, and power dissipation. Finally, it introduces one-shot monostable multivibrators, covering their circuit behavior, timing, and the difference between non-retriggerable and retriggerable types.

📝 Lecture Summary

Asynchronous Preset and Clear Inputs

Synchronous inputs (S-R, J-K, D) only affect the output when a clock transition occurs. Asynchronous inputs (Preset and Clear) change the output to a known logic level independently of the clock. The PRE (Preset) input sets Q=1 and Q̅=0 when set to 0; the CLR (Clear) input sets Q=0 and Q̅=1 when set to 0. These inputs override the synchronous inputs. To use the flip-flop in synchronous mode, PRE and CLR must both be set to logic 1. Setting both PRE and CLR to 0 is invalid. 💡 Why this matters: Asynchronous inputs are essential for initializing flip-flops to a known state before a circuit begins operation.

🔑 Definition — Asynchronous Inputs: Inputs that change the output of a flip-flop to a known logic level independently of the clock signal.

📐 Truth Table (J-K flip-flop with Async Inputs):

• PRE=0, CLR=0 → Invalid
• PRE=0, CLR=1 → Q(t+1)=1
• PRE=1, CLR=0 → Q(t+1)=0
• PRE=1, CLR=1 → Clocked operation (synchronous inputs J-K determine output)

📌 Example: To preset a J-K flip-flop to Q=1, set PRE=0 and CLR=1. PRE=0 sets Q to 1; CLR=1 allows Q̅ to be set to 0 via the NAND gate network. Inputs J and K have no effect.

The 74HC74 Dual Positive-Edge triggered D flip-flop

This is an Integrated Circuit containing two positive-edge triggered D flip-flops. Each flip-flop has independent clock inputs, synchronous inputs, and asynchronous Preset and Clear inputs.

The 74HC112 Dual Positive-Edge triggered J-K flip-flop

This is an Integrated Circuit containing two positive-edge triggered J-K flip-flops. Each flip-flop has independent clock inputs, synchronous inputs, and asynchronous Preset and Clear inputs.

Master-Slave Flip-Flops

Master-Slave flip-flops are now obsolete, replaced by edge-triggered flip-flops. They consist of two stages: a Master and a Slave, both are Gated S-R flip-flops. The Master is enabled during the positive half of the clock cycle; the Slave is enabled during the negative half. It is a pulse-triggered flip-flop. During the positive half, the Master accepts inputs; its outputs remain fixed during the negative half. During the negative half, the Slave copies the Master's outputs, and the Master is disabled. This setup synchronizes the operation with a common clock signal.

🔑 Definition — Master-Slave Flip-Flop: A flip-flop composed of two gated S-R flip-flops (Master and Slave) where the Master is enabled during the positive clock half and the Slave during the negative half, creating a pulse-triggered operation.

📐 Truth Table (Master-Slave J-K flip-flop):

• CLK= Pulse, J=0, K=0 → Q(t+1)=Q(t)
• CLK= Pulse, J=0, K=1 → Q(t+1)=0
• CLK= Pulse, J=1, K=0 → Q(t+1)=1
• CLK= Pulse, J=1, K=1 → Q(t+1)=Q̅(t)

Flip-Flop Operating Characteristics

The performance of a flip-flop is specified by several operating characteristics found in manufacturer data sheets. These include: Propagation Delay, Set-up Time, Hold Time, Maximum Clock Frequency, Pulse Width, and Power Dissipation.

🔑 Definition — Propagation Delay: The interval of time between when an input is applied and when the output changes. There are four types: clock to low-to-high (t_PLH), clock to high-to-low (t_PHL), preset to low-to-high (t_PLH), and clear to high-to-low (t_PHL). Measurements are taken at the 50% transition marks of both the triggering edge and the resulting output change.

🔑 Definition — Set-up Time (t_s): The minimum time required for the input logic levels to remain stable before the clock transition occurs for the flip-flop to reliably change its output state.

🔑 Definition — Hold Time (t_h): The minimum time for which the input signal must be maintained after the clock transition for the flip-flop to reliably clock in the input signal.

🔑 Definition — Maximum Clock Frequency (f_max): The highest rate at which the flip-flop operates reliably. Exceeding this frequency causes the flip-flop to malfunction.

🔑 Definition — Pulse Width (t_w): The minimum specified duration for the clock, preset, and clear signals to ensure correct flip-flop operation. The clock signal has separate minimum high and low time specifications.

🔑 Definition — Power Dissipation (P): The power consumed by a flip-flop during operation, calculated as P = V_cc × I_cc. Example: A flip-flop connected to +5V drawing 5mA dissipates 25 mW. This is critical for selecting an appropriate DC power source for a digital circuit.

One-Shot (Monostable Multivibrator)

A monostable multivibrator has one stable state and one unstable state. When triggered, it temporarily enters the unstable state for a predetermined time determined by an external R-C time constant (RC), then automatically returns to the stable state. The output is a pulse of duration determined by R and C. Two types exist: Nonretriggerable and Retriggerable.

🔑 Definition — One-Shot: A monostable device that produces a single output pulse of a fixed duration when triggered.

📌 Example: In a basic One-Shot circuit, a triggering pulse at time t1 sets the NOR gate output to low, inverting to high via NOT gate. This high output feeds back to maintain the low NOR output. Capacitor C charges through resistor R. When fully charged at time t2, the NOT gate input goes high, setting its output low and returning the One-Shop to its stable state. The unstable time interval is from t1 to t2, determined by the RC time constant.

1. Nonretriggerable One-Shot

A nonretriggerable One-Shot, once triggered into its unstable state, remains there for a fixed period regardless of any new trigger inputs. It must return to its stable state before it can be triggered again. The duration of input trigger pulses has no effect on the output pulse duration.

2. Retriggerable One-Shot

A retriggerable One-Shot is similar to a nonretriggerable One-Shot, except it can be retriggered even while in its unstable state. If a new trigger is applied, the output pulse is extended from the time of the new trigger.

⭐ Key Takeaways

Asynchronous Preset and Clear inputs are critical for initializing flip-flops to known states (Q=1 or Q=0) independently of the clock, overriding synchronous inputs. Master-Slave flip-flops use a two-stage pulse-triggered architecture with Master enabled on the positive half cycle and Slave on the negative half. Six key flip-flop operating characteristics define performance: propagation delays (clock, preset, clear to output transitions), set-up time, hold time, maximum clock frequency, minimum pulse widths, and power dissipation. A one-shot monostable multivibrator produces a single output pulse of a fixed duration determined by an external R-C time constant, with non-retriggerable types ignoring new triggers while unstable and retriggerable types extending the pulse with each new trigger.

🧠 Quick Revision Questions

1. What is the difference between synchronous and asynchronous inputs in a flip-flop, and how do Preset and Clear inputs function?
2. Explain the operation and timing of a Master-Slave J-K flip-flop, including which stage is enabled during the positive and negative half cycles.
3. Define propagation delay, set-up time, and hold time for a flip-flop, and explain why each is important for reliable operation.
4. What is the purpose and formula for calculating power dissipation in a flip-flop, and why is it important in digital circuit design?
5. Describe the difference between a nonretriggerable and a retriggerable one-shot, including how each responds to trigger inputs while in the unstable state.

📘 Lecture 26 — THE 555 TIMER

📖 Overview: This lecture covers timing problems in synchronous digital circuits, including clock skew and race conditions. It then introduces counters, focusing on asynchronous (ripple) counters, their operation, propagation delay issues, and how to design Mod-n counters using flip-flops and integrated circuits like the 74LS93A.

🗂️ Topics Covered

The lecture begins with the timing problem in flip-flop circuits using J-K flip-flops and a common clock. It then explains clock skew and its intermittent effects, followed by race conditions and glitches. The main focus shifts to counters, starting with their classification into asynchronous and synchronous types. Asynchronous counters (ripple counters) are detailed with 3-bit up-counter circuits, timing diagrams including propagation delay, and the limitations at high frequencies. The concept of Mod-n counters is introduced, with examples of a Mod-6 counter and a Mod-10 decade counter. Finally, the 74LS93A integrated circuit asynchronous counter is presented, showing how to configure it as Mod-16, decade, and cascaded frequency dividers.

📝 Lecture Summary

Timing Problem in flip-flop circuits

In synchronous digital circuits, the output of one flip-flop is connected to the input of a second, with both triggered by a common clock. This can cause a timing problem. For example, when a high-to-low clock transition occurs, the first flip-flop's output begins to change after a propagation delay (tPHL). The input to the second flip-flop must be held stable for its hold time (tH). If the propagation delay of the first flip-flop is less than the hold time requirement of the second, the second flip-flop's output cannot be guaranteed. However, most practical flip-flops have hold times of 5 nsec or less, often 0, so such circuits generally work reliably.

Clock Skew

Clock Skew is a common problem where the same clock signal arrives at different clock inputs at different times due to propagation delays through gates. This can cause different flip-flops to change states asynchronously, leading to unpredictable outputs. For example, if a NAND and NOT gate delay the clock to one flip-flop, the clock skew is the time difference between the two clock signals. If a flip-flop's propagation delay (tPLH) is less than the skew, the next flip-flop will see the changed input at its delayed clock edge, leading to an incorrect state change. If the propagation delay is longer than the skew, the next flip-flop remains unchanged. Timing issues from clock skew are intermittent and difficult to detect, as skew varies with temperature, voltage, and loading. Problems can be eliminated by equalizing clock delays.

Race Conditions

Race conditions occur when multiple internal variables change due to a change in one input variable. Depending on the sequence of these changes, the circuit output operates erratically. In a timing diagram, if the Q and Q̅ outputs' transitions are slightly delayed, they can coincide with clock transitions, generating short-duration pulses called glitches. These glitches are difficult to detect. Glitches due to race conditions can be avoided by using a negative-edge triggered flip-flop instead of a positive-edge-triggered one.

Counters

Counter circuits based on flip-flops are widely used in digital systems for counting, frequency division, and as shift registers. Counters are classified into two types. Asynchronous counters do not have all flip-flops triggered simultaneously; only the first receives the clock, and subsequent flip-flops are triggered by the outputs of previous ones. Synchronous counters have all flip-flop clock inputs connected to a common clock, so they receive the clock signal simultaneously. Both types are further classified as up counters or down counters based on their counting sequence.

Asynchronous Counters (Ripple Counters)

Asynchronous counters, also known as Ripple Counters, are implemented by connecting multiple flip-flops where the clock signal is applied only to the first. The Q or Q̅ output of each flip-flop provides the clock for the next. As the clock "ripples" through the chain, outputs change one after another. In a 3-bit Asynchronous Up-Counter, all J-K inputs are tied high for toggling. The first flip-flop (F0) toggles on every high-to-low clock transition. The second (F1) toggles on every high-to-low transition of F0. The third (F2) toggles on every high-to-low transition of F1. The outputs cycle through 8 unique states (0 to 7), acting as a Mod-8 counter.

🔑 Definition — Asynchronous Counter: A counter where the flip-flops are not clocked simultaneously; the clock input of each flip-flop is driven by the output of the preceding flip-flop.

📐 Formula for number of states: 2^m → The maximum number of unique states for a counter with m flip-flops is 2 raised to the power of m. 📌 Example: A 3-bit counter has 2^3 = 8 unique states (000 to 111).

Propagation Delay

The timing diagram of a 3-bit asynchronous counter must account for propagation delay. When the clock transitions, F0 toggles after a delay (tPHL). This transition then causes F1 to toggle after its own delay, and so on. The total delay for the last flip-flop (F2) is the sum of the propagation delays of all three flip-flops. If the counter is extended with more flip-flops, the total delay might exceed the clock period, causing timing problems. Asynchronous counters cannot operate at very high clock frequencies and can cause issues with decoding circuits.

📐 Formula: Total Delay for last FF = Sum of all individual FF propagation delays → The time for the final output to stabilize is the cumulative sum of delays in the chain. 📌 Example: With high frequency, at interval t4, a clock transition toggles F0 after tPHL. This delayed transition toggles F1 after its tPHL, and that transition toggles F2 after its tPLH. The result is that at interval t5, the output is 010 instead of the intended 100, showing an incorrect count.

🔑 Definition — Propagation Delay: The time it takes for a change at the input of a flip-flop to appear at its output, denoted as tPHL (high to low) and tPLH (low to high).

Mod-n Counters

The Modulus (Mod) of a counter is the total number of unique states in its counting sequence. While a standard m-bit counter has 2^m states, counters can be designed to have a truncated sequence with fewer states. This is done by resetting the counter to 0 when it reaches the intended last state. The reset is achieved by connecting the active-low Clear (CLR) inputs of all flip-flops to the output of a combinational circuit (e.g., a NAND gate). This circuit activates (goes low) when it detects the specific count value that should trigger the reset.

🔑 Definition — Modulus (Mod): The number of unique states through which a counter sequences before it repeats. 📌 Example: A Mod-6 Counter uses three flip-flops but only counts from 000 to 101 (6 states). When it reaches state 110, the NAND gate outputs a low signal, resetting all flip-flops to 000. The output frequency at F2 is 1/6th of the input clock frequency.

📐 Formula: Output Frequency = Input Clock Frequency / Modulus → The counter divides the input clock frequency by its Mod number. 📌 Example: A Mod-6 counter divides the clock frequency by 6.

Mod-10 Counter (Decade Counter)

A Decade Counter is a Mod-10 counter that uses four flip-flops to count through 10 unique states (0000 to 1001). It is reset when it would normally count to the next state, 1010. The outputs F1 and F3 are connected to a NAND gate, which resets all flip-flops to 0000 when both are logic 1 (detecting 1010). The output frequency is 1/10th of the input clock frequency.

📌 Example: The decade counter counts 0, 1, 2, ..., 9. Upon the 10th input pulse, it resets to 0. The output signal at the most significant bit has a frequency equal to the input frequency divided by 10.

Integrated Circuit Asynchronous Counters

The 74LS93A is a 4-bit asynchronous counter IC. It has two clock inputs (CLKA and CLKB) and two reset inputs (RO1 and RO2) that are inputs to an internal NAND gate, which is connected to the clear inputs of all four flip-flops. By connecting the IC pins in different ways, various counter configurations can be made:

• MOD-16 Counter: Connect CLKB to Q0 output. This makes the four flip-flops a single 4-bit binary counter.
• Decade Counter: Connect CLKB to Q0. Connect Q1 and Q3 to RO1 and RO2. This creates a MOD-10 counter.
• Cascading for Frequency Division: Two 74LS93A ICs can be cascaded to create larger counters. For example, a divide-by-50 counter is made by configuring the first IC as a MOD-10 counter and the second as a MOD-5 counter, then connecting the Q3 output of the first to the CLKB input of the second.

📌 Example: A divide-by-50 counter uses two 74LS93A ICs. The first divides the input clock by 10, and its output drives the second IC which divides by 5, resulting in an output that is 1/50th of the original input frequency.

⭐ Key Takeaways

The most critical concepts from this lecture are the timing problems in synchronous circuits, specifically clock skew and race conditions, which can cause intermittent and glitchy behavior. The core learning is the operation of asynchronous counters, where the clock "ripples" through flip-flops, leading to a cumulative propagation delay that limits their maximum speed. You must understand the concept of the Modulus (Mod) of a counter and how to design truncated sequences (like a Mod-6 or Decade counter) by using feedback to reset the counter at a desired state. Finally, you should be able to explain how a standard IC like the 74LS93A can be configured for different Mod numbers and how multiple ICs can be cascaded to create larger frequency dividers.

🧠 Quick Revision Questions

1. What is clock skew, and why does it cause intermittent timing problems in synchronous circuits?
2. Explain why asynchronous counters are also called "ripple counters" and describe the main disadvantage of this architecture regarding propagation delay.
3. How many flip-flops are needed for a Mod-12 counter, and what is the formula to determine this number?
4. Describe the process of creating a truncated sequence counter (e.g., a Mod-6 counter) using the asynchronous clear (CLR) inputs of flip-flops.
5. Explain how you would configure a single 74LS93A IC to function as a decade (Mod-10) counter. Which pins must be externally connected?

📘 Lecture 27 — DOWN COUNTERS

📖 Overview: This lecture introduces down counters, which count downward from a maximum value to zero, and explains how they are implemented using J-K flip-flops with Q outputs connected to subsequent flip-flops. It also covers synchronous counters, which use a common clock signal to eliminate propagation delay issues, enabling reliable high-frequency operation for multi-bit counting applications.

🗂️ Topics Covered

The lecture covers 3-bit asynchronous down-counters and their timing diagrams, down-counters configured to count truncated sequences by presetting to maximum rather than clearing, synchronous counters with common clock input for simultaneous flip-flop triggering, 3-bit and 4-bit synchronous binary counters with AND gates for proper sequencing, and a synchronous decade counter using logic gates to reset after reaching state 1001.

📝 Lecture Summary

3-bit Asynchronous Down-Counter

A down counter counts in a sequence starting with some maximum count value and counts down to binary zero, then resets to the maximum value and repeats. It is implemented by connecting the Q output instead of the Q output of all flip-flops to the clock inputs of the next flip-flops. In Figure 27.1, the 3-bit asynchronous down-counter uses negative edge-triggered J-K flip-flops with F₀'s Q output driving F₁'s clock input, and F₁'s Q output driving F₂'s clock input. The timing diagram shows the counter progressing from 111 down to 000 and then repeating, with each flip-flop toggling on the negative transition of its clock input.

🔑 Definition — Down Counter: A counter that counts downward from a maximum value (e.g., 111) to binary zero, then resets to the maximum and repeats the sequence.

📌 Example: In Figure 27.1b, at t₁, F₀ toggles from 0 to 1 (Q=1); at t₂, F₀ toggles to 0 (Q=0) which causes F₁ to toggle from 0 to 1; at t₃, F₀ toggles to 1; at t₄, F₀ toggles to 0 causing F₁ to toggle to 0 and F₂ to toggle to 1 (since F₁'s Q output transitions from 1 to 0). The sequence continues: t₅=011, t₆=010, t₇=001, t₈=000, then repeats at t₉=111.

💡 Why this matters: Down counters are essential for applications requiring countdown timers, such as real-time clocks, industrial controllers, and digital stopwatches.

Down Counter with Truncated Sequence

A down counter with truncated sequence counts down from the maximum count value to some predefined last count value. On reaching the last count value, the down-counter is preset to the maximum count value (instead of being cleared to zero as in up-counters). Figure 27.2a shows a 3-bit down-counter configured to count down from 111 to 011. When the counter reaches 011 and decrements to 010, the NAND gate outputs logic 0, which presets all three flip-flops to 111. The counter then continues from 111 down to 110 and 101.

🔑 Definition — Truncated Sequence Down Counter: A counter that counts down from maximum to a predefined lower value, then presets back to maximum rather than clearing to zero.

📌 Example: In Figure 27.2b, the counter counts: t₁=111, t₂=110, t₃=101, t₄=100, t₅=011. At t₆, it would go to 010 but instead F₀, F₁, and F₂ are set to 111 via presetting. The sequence continues: t₇=110, t₈=101 (the counter repeats every 5 clock pulses instead of 8).

Synchronous Counters

Synchronous counters use a common clock signal connected to the clock inputs of all counter flip-flops, so on a clock transition all flip-flops change their output state simultaneously. This eliminates timing problems caused by excessive propagation delays in asynchronous counters, especially for 8, 16, and 32-bit applications operating at high clock frequencies. Figure 27.3a shows a 2-bit synchronous counter where both J-K flip-flops share the same clock input. The J-K inputs of the second flip-flop are connected to the Q output of the first flip-flop.

🔑 Definition — Synchronous Counter: A counter where all flip-flops are simultaneously triggered by a common clock signal, eliminating rippling delays.

💡 Why this matters: Synchronous counters are essential for high-speed digital systems like microprocessors, where precise timing is critical and propagation delays cannot be tolerated.

📌 Example: In Figure 27.3b, at t₁, F₀ toggles to 1 (since J=K=1) while F₁ remains 0 (since its J-K inputs were 0 at the clock transition). At t₂, F₀ toggles to 0 and F₁ toggles to 1 (since F₀'s previous high output made J-K of F₁=1). At t₃, F₀ toggles to 1 but F₁ stays 1 (since F₀'s output changed after the clock edge). At t₄, both toggle: F₀ to 0 and F₁ to 0.

3-bit & 4-bit Synchronous Counters

Multi-bit synchronous counters larger than 2 bits require an AND gate. Figure 27.4a shows a 3-bit synchronous counter where the outputs F₀ and F₁ are connected to a 2-input AND gate, whose output connects to the J-K inputs of the third flip-flop. This ensures the third flip-flop toggles only when both F₀ and F₁ are logic 1, which occurs at intervals t₄ (011→100) and t₈ (111→000). Without the AND gate, if F₁ directly drove the third flip-flop, F₂ would toggle at t₃ when only F₁ is high, disturbing the count sequence.

A 4-bit synchronous binary counter uses four flip-flops. The fourth flip-flop's J-K inputs connect through a 3-input AND gate with inputs F₀, F₁, and F₂. The fourth flip-flop changes state only when outputs of the first three flip-flops are all logic 1, occurring when counting from 0111 to 1000 and from 1111 to 0000.

🔑 Formula: J-K₃ = F₀ · F₁ (for 3-bit counter) → The third flip-flop toggles only when F₀ AND F₁ are both 1 J-K₄ = F₀ · F₁ · F₂ (for 4-bit counter) → The fourth flip-flop toggles only when F₀ AND F₁ AND F₂ are all 1

📌 Example: In Figure 27.4b, at t₁: F₀=1, F₁=0, F₂=0. At t₂: F₀=0, F₁=1, F₂=0. At t₃: F₀=1, F₁=1, F₂=0 (AND gate output=0 because F₁ just became 1). At t₄: F₀=0, F₁=0, F₂=1 (both F₀ and F₁ were 1 just before, so AND gate output=1 enabled F₂ to toggle).

4-bit Synchronous Decade Counter

A synchronous decade counter counts from 0000 to 1001 (0 to 9) and then resets to 0000. Instead of using clear asynchronous inputs, logic gates reset the counter after reaching state 1001. The J-K inputs are determined by Boolean expressions derived from the function table (Table 27.1):

• F₀: J-K connected to logic high (toggles every clock)
• F₁: J-K = F₀ · F₃' (toggles when F₀=1 AND F₃=0)
• F₂: J-K = F₀ · F₁ (toggles when both F₀ and F₁ are 1)
• F₃: J-K = F₀ · F₁ · F₂ + F₀ · F₃ (toggles when all three lower bits are 1 OR when F₀ and F₃ are both 1)

🔑 Definition — Synchronous Decade Counter: A synchronous counter that counts from 0000 to 1001 (ten states) using logic gates for the J-K inputs instead of asynchronous clear inputs.

📌 Example: At clock pulse 9, the state is 1001 (F₃=1, F₂=0, F₁=0, F₀=1). At clock pulse 10, the counter should go to 0000. The expression F₀·F₃ becomes 1·1=1 for F₁, which would normally cause F₁ to toggle, but since F₁=0 and the expression also depends on F₃, the overall logic resets F₃ to 0 and F₁ remains 0, achieving the decade transition.

⭐ Key Takeaways

Down counters are implemented using Q outputs rather than Q outputs to achieve downward counting. Truncated sequence down counters use presetting to maximum instead of clearing to zero when reaching the last count. Synchronous counters eliminate propagation delay issues by using a common clock for all flip-flops, enabling high-frequency operation. For synchronous counters larger than 2 bits, AND gates are essential to ensure proper timing of higher-order flip-flop toggling. The synchronous decade counter achieves 0-9 counting using carefully designed Boolean expressions for each flip-flop's J-K inputs, resetting after state 1001 without relying on asynchronous clear inputs.

🧠 Quick Revision Questions

1. What is the key difference in flip-flop output connections between an up-counter and a down-counter?
2. In a truncated sequence down counter, what happens when the counter reaches its last count value?
3. Why do synchronous counters require AND gates for 3-bit and larger implementations?
4. What Boolean expression controls the J-K inputs of the fourth flip-flop in a synchronous decade counter?
5. Why are synchronous counters preferred over asynchronous counters for high-frequency applications with multiple bits?

📘 Lecture 28 — Timing Diagram of a Synchronous Decade Counter

📖 Overview: This lecture explores the timing behavior and implementation of synchronous decade counters and Mod-n counters using integrated circuits. It covers cascading counters for larger count sequences, configuring IC counters with truncated sequences, and the operation of up-down counters, which are essential for building practical digital counting systems.

🗂️ Topics Covered

The lecture covers Mod-n synchronous counter design, the 74HC163 4-bit synchronous counter IC and its timing diagram, the 74HC160 decade counter, cascading counters using enable inputs and RCO outputs, configuring IC counters as Mod-n counters with truncated sequences using load and clear methods, cascaded counters with truncated sequences, and the implementation of up-down counters.

📝 Lecture Summary

Timing Diagram of a Synchronous Decade Counter

A synchronous decade counter uses J-K flip-flops with simultaneous clock triggering to count a truncated sequence of ten unique states (0000 to 1001). The timing diagram shows how the counter outputs (F0, F1, F2, F3) change at each clock transition from t1 to t10, completing one full decade cycle. The Modulus number represents the unique number of states, and the number of flip-flops required is determined by the relation n = 2^m, where m is the number of flip-flops.

Mod-n Synchronous Counter

A Mod-n Synchronous Counter can be implemented using an appropriate number of J-K flip-flops connected together with their clocks triggered simultaneously. A synchronous counter which counts a truncated sequence of n unique states can be similarly implemented.

🔑 Definition — Modulus number: The unique number of states which the counter counts in a sequence.

📐 Formula: n = 2^m → The Modulus number (n) equals 2 raised to the power of m, where m is the number of flip-flops.

Integrated Circuit Synchronous Counters

Instead of connecting a large number of flip-flops together to form large synchronous counters, counter circuits available in Integrated Circuit form can be quickly connected. The 74HC163 is a 4-bit Synchronous Counter with the following pins:

1. Parallel data inputs D0, D1, D2 and D3
2. Data outputs Q0, Q1, Q2 and Q3
3. Positive edge-triggered CLOCK signal
4. Active-low CLR input which resets the Counter output to 0000
5. Active-low LOAD input which loads the 4-bit data applied at the counter inputs
6. Active-high ENT and ENP enable inputs — for the counter to operate both must be high
7. The RCO (Ripple Clock Output) goes high when the Counter reaches the terminal count 1111. The RCO output along with ENT and ENP enable input pins are used to cascade multiple counter ICs.

Referring to the timing diagram, the CLR signal is activated between interval t0 and t1. The counter output is reset synchronously at interval t1 as the CLR signal is active at interval t1. The LOAD signal is activated between interval t1 and t2. At the clock transition at t2, the counter is loaded with the 4-bit data. The ENP and ENT enable signals are activated before interval t3 and the counter increments at clock transitions at t3 and t4. When the counter reaches count 15 at interval t4, the RCO is set to high. At intervals t5, t6, t7 and t8 the counter counts to 0, 1, 2 and 3. The enable signal ENP is deactivated after interval t8, inhibiting further counting.

The 74HC160 is a 4-bit Synchronous Decade counter with the same pins as the 74HC163. The RCO output of the decade counter is activated when the counter reaches its terminal count 1001.

💡 Why this matters: These IC counters simplify building large counting systems by providing ready-made, cascadable modules with clear, load, and enable functions.

Cascading Counters

It is very convenient to cascade Integrated Circuit counters together to form larger counters. The enable inputs and RCO outputs allow cascading of multiple counters. Two 74HC160 decade counters can be connected together to divide the input frequency by 10 and 100.

In the timing diagram, at interval t9 the first decade counter reaches terminal count 1001. The RCO output of the first counter is set to logic 1. The RCO of the first counter is connected to the ENP and ENT enable pins of the second counter, so the second counter is enabled. At interval t10 on a positive clock transition, the first counter increments to 0000. Since the second counter is also enabled, it increments to 0001. As soon as the first counter goes to 0000, the RCO signal is deactivated, inhibiting the second counter. The first counter counts from 0001 to 1000 in intervals t11 to t19. At interval t19, the first counter again reaches terminal count 1001, the RCO becomes active, activating the second counter. At interval t20, the first and second counters increment to 0000 and 0010 respectively. The RCO is again deactivated. This sequence continues.

Integrated Circuit Counters with Truncated Sequences

A decade counter can be implemented by truncating the counting sequence of a MOD-16 counter. The 74HC163 can be configured as a Mod-7 counter. The counter is preset with the count value 1001 by setting the LOAD/NORMAL input to logic 1 at the NOR gate input. At the positive clock transition t1, the count value is loaded. The counter increments and at interval t7 it reaches the terminal count. The RCO output is set to logic 1 which sets the LOAD input to logic 0. At the positive clock transition at interval t8, the preset value 1001 is reloaded.

Another method to configure an IC counter is to reset the counter when it reaches the maximum count value of its truncated sequence. This requires extra logic gates that determine the terminating state and reset the counter. The 74HC161 has an Asynchronous Clear input, whereas the 74HC163 has a synchronous Clear input. At time interval t9, the counter increments to 1001 which sets the AND gate output to logic 1. The NOR gate output goes low, activating the clear input and resetting the counter to 0000. The 74HC163 with synchronous clear would reset at interval t10 when there is a clock transition.

📌 Example: To implement a Mod-9 counter, the 74HC161 (with asynchronous clear) must be used instead of the 74HC163 (with synchronous clear) because the clear must occur immediately when count 1001 is reached, not at the next clock edge.

Cascaded Counters with Truncated Sequences

Three cascaded 74HC163 counters can be configured to count in a truncated sequence. The 12-bit cascaded counter is loaded with initial count value 1000 0000 0000. When the counter counts to 1111 1111 1111, the RCO output set to logic 1 by the third counter reloads the initial count values 0000, 0000 and 1000 in all three counters. The 12-bit counter can be configured for maximum count sequence as Modulus 4096 counter. The counter has been configured to count from 1000 0000 0000 to 1111 1111 1111, which is 2048 states or Modulus 2048 counter.

Up-Down Counter

An up-down counter can increment its output count value at each clock transition or decrement its count value at each clock transition, depending upon the count mode. The counter can be reconfigured during its count sequence.

🔑 Definition — Up-Down Counter: A counter that can either increment (up-count) or decrement (down-count) its output at each clock transition.

For the up-counting sequence of a 3-bit synchronous counter, from Clock Pulse 0 to 7, the outputs Q2, Q1, Q0 count from 000 to 111. For the down-counting sequence, from Clock Pulse 0 to 7, the outputs count from 111 to 000.

For the down-counting sequence, the output Q0 of the first flip-flop toggles between 0 and 1, therefore the J-K inputs are connected to logic 1. The output Q1 of the second flip-flop toggles when Q0 output is logic 0 or Q0 is logic 1. The output Q2 of the third flip-flop toggles when Q0 and Q1 outputs are both logic 0 or both logic 1.

📐 Observation for down-counter: Q0 toggles always (J=K=1); Q1 toggles when Q0=0; Q2 toggles when Q0 and Q1 are both 0. This is the complement condition compared to the up-counter.

⭐ Key Takeaways

The 74HC163 is a 4-bit synchronous counter with synchronous clear, while the 74HC161 has asynchronous clear — this difference is critical when designing truncated counters where immediate reset at a specific count is required. Cascading counters using RCO and enable pins allows building larger counters efficiently, and truncated sequences can be achieved either by loading a preset value when the terminal count is reached or by clearing the counter asynchronously at the desired maximum count. Up-down counters combine both counting directions using J-K inputs that toggle based on different conditions for up and down modes. The modulus of a counter determines the number of flip-flops needed via the relation 2^m ≥ n.

🧠 Quick Revision Questions

1. What is the difference between synchronous and asynchronous clear inputs, and why does this matter when designing a Mod-9 counter using IC counters?
2. How does the RCO output function when cascading two 74HC160 decade counters, and what happens at the moment the first counter reaches terminal count?
3. In a 3-bit up-down counter, what condition must be true for Q1 to toggle in down-counting mode versus up-counting mode?
4. How is a 74HC163 configured as a Mod-7 counter using the LOAD input and RCO output?
5. What is the relationship between the number of flip-flops (m) and the maximum modulus (n) of a counter, and how is a truncated sequence implemented?

📘 Lecture 29 — UP/DOWN COUNTER

📖 Overview: This lecture covers the design and implementation of synchronous up/down counters, including the 74HC190 integrated circuit counter. It explains counter decoding techniques, the problem of glitches and their elimination through strobing, and presents practical applications such as digital clocks and frequency counters. The lecture concludes with a systematic design procedure for sequential circuits (state machines) using state diagrams, next-state tables, Karnaugh maps, and logic implementation.

🗂️ Topics Covered

The lecture covers synchronous down-counters and their similarity to up-counters, the implementation of a combined up/down counter with additional logic, and the 74HC190 4-bit synchronous up/down counter IC. It discusses counter decoding using AND/NAND gates, the problem of decoder glitches due to propagation delays, and the strobing method to eliminate glitches. Practical counter applications include a digital clock circuit using divide-by-60 counters and a frequency counter circuit. The lecture also details the systematic design procedure for sequential circuits, including state diagrams, next-state tables, flip-flop transition tables, Karnaugh maps, and logic implementation, specifically for a 3-bit up/down counter.

📝 Lecture Summary

DOWN COUNTER

The down-counter is implemented by connecting the AND gate to the complementary outputs (Q̅) of the first and second flip-flops instead of the Q outputs used in an up-counter. The circuit is very similar to the up-counter, with the only change being the connection of the AND gate to the Q̅0 and Q̅1 outputs. When Q0 is logic 0, Q̅0 is logic 1, enabling the next flip-flop to toggle. Similarly, when both Q0 and Q1 are logic 0, Q̅0 and Q̅1 are logic 1, enabling flip-flop 3 to toggle.

UP/DOWN COUNTER

The up-counter and down-counter can be implemented as a single counter circuit by adding extra logic. In this circuit, the UP/DOWN input is set to logic 1 to count up or logic 0 to count down. When the UP/DOWN input is logic 1, the upper AND gates are enabled, allowing flip-flops to toggle based on the Q outputs (up-counting). When the UP/DOWN input is logic 0, the lower AND gates are enabled, allowing flip-flops to toggle based on the Q̅ outputs (down-counting). The UP/DOWN input can be changed at any time during the counting sequence to reverse the direction.

74HC190 INTEGRATED CIRCUIT UP/DOWN DECADE COUNTER

The 74HC190 is a 4-bit synchronous up/down counter available as an integrated circuit. It features parallel data inputs (D₀–D₃), data outputs (Q₀–Q₃), a positive edge-triggered clock, an active-low LOAD input, an active-low CTEN (counter enable) input, a D/U (down/up) input to select counting direction, a MAX/MIN output that goes high when the terminal count (1001 for up, 0000 for down) is reached, and a RCO (ripple clock output) that goes low at the terminal count during the negative half of the clock cycle. The RCO and MAX/MIN outputs, along with the CTEN input, are used to cascade multiple counter ICs for larger counters.

🔑 Definition — CTEN: Counter enable input; when active-low, it enables the counter to count. 🔑 Definition — RCO: Ripple clock output; goes low when the counter reaches the terminal count (1001 counting up or 0000 counting down), remaining low during the negative half of the clock cycle. Used for cascading counters.

COUNTER DECODING

Counter decoding uses decoders or logic gates to determine when a counter is in a specific state. For example, a decoder can be implemented using AND or NAND gates to detect outputs like 0100 (4), 1000 (8), and 1100 (12) from a 4-bit counter. The propagation delay due to the ripple effect in asynchronous counters and slight variations in propagation delays in synchronous counters can cause glitches — short, spurious pulses at decoder outputs.

💡 Why this matters: Glitches can cause erratic behavior in digital circuits that rely on decoded counter outputs for sequencing.

Glitches can be eliminated by using the strobing method, where a clock signal is used to enable the decoder gates after the glitches have settled. The decoder gates are enabled only during the second, positive half of the clock signal, while they are disabled during the first negative half when glitches occur. This allows the decoder outputs to be activated only after a delay, ensuring stable outputs.

COUNTER APPLICATIONS

1. Digital Clock: A digital clock is implemented using the AC 50 Hz frequency as the clock signal. The circuit includes a divide-by-50 counter to generate a 1 Hz signal, divide-by-60 counters for seconds and minutes (counting 0 to 59), and a decade counter with a flip-flop for hours (counting 1 to 12). The divide-by-60 counter is implemented by cascading two 74HC160A decade counters — a units counter (0000 to 1001) and a tens counter configured as a Mod-6 counter (000 to 101). A NAND gate detects the count 110 to reset the tens counter to 000. The hours counter uses a single decade counter and a J-K flip-flop, counting 12 unique states.

2. Frequency Counter: A frequency counter measures the frequency of an input signal by counting clock pulses in a predetermined time interval. The frequency (Hz) equals the number of clock pulses counted divided by the sampling interval (seconds). The circuit uses an AND gate to pass the input signal to the counter during a sampling interval. The accuracy of the frequency counter depends on the accuracy of the sampling interval, which is implemented using cascaded counters connected to a crystal-controlled oscillator. A J-K flip-flop divides the timing signal by 2 to control the sampling interval.

💡 Why this matters: The longer the sampling interval, the more accurate the frequency measurement, as fewer pulses are missed or counted incorrectly due to the start and stop of the sampling window.

DESIGN OF SYNCHRONOUS COUNTERS

A general sequential circuit (state machine) consists of a combinational circuit and a memory circuit (flip-flop). The present state of the memory is represented by state variables, and on a clock transition, the memory changes to the next state, determined by excitation inputs. The design procedure follows six steps.

Design Procedure Steps:

1. State Diagram: Shows the sequence of states through which the sequential circuit progresses when clocked.
2. Next-State Table: Lists each present state and the corresponding next state.
3. Flip-flop Transition Table: Lists all possible flip-flop input combinations that allow the present state to change to the next state on a clock transition.
4. Karnaugh Maps: For each state variable, J-K inputs are mapped from the next-state table and transition table.
5. Logic expressions for Flip-flop Inputs: Simplified Boolean expressions are obtained from the Karnaugh maps.
6. Sequential Circuit Implementation: The Boolean expressions are implemented using logic gates and flip-flops.

IMPLEMENTING A 3-BIT UP/DOWN COUNTER

Step 1 - State Diagram: A state diagram for a 3-bit up/down counter shows that when input X=0, the counter counts up (000 → 001 → 010 → ... → 111 → 000), and when X=1, it counts down (000 → 111 → 110 → ... → 001 → 000).

Step 2 - Next-State Table: The next state table lists present states and next states for both X=0 and X=1. For example, present state 000 has next state 001 for X=0 and 111 for X=1.

Step 3 - Flip-flop Transition Table: Using the J-K flip-flop transition table, the J and K inputs required for each state transition are determined for both X=0 and X=1.

Step 4 - Karnaugh Maps: The J and K inputs for each flip-flop are mapped to 4-variable Karnaugh maps (with variables Q₂, Q₁, Q₀, and X).

Step 5 - Logic expressions for Flip-flop Inputs: From the Karnaugh maps, the simplified Boolean expressions are:

• J₂ = Q₁Q₀X̅ + Q̅₁Q̅₀X
• K₂ = Q₁Q₀X̅ + Q̅₁Q̅₀X
• J₁ = Q₀X̅ + Q̅₀X
• K₁ = Q₀X̅ + Q̅₀X
• J₀ = 1
• K₀ = 1

Step 6 - Sequential Circuit Implementation: The Boolean expressions are implemented using logic gates and three J-K flip-flops. The X input (up/down control) is connected to the gates along with the Q outputs to create the correct counting sequence.

🔑 Definition — State variables: Variables (Q outputs of flip-flops) that represent the present state of the memory in a sequential circuit. 🔑 Definition — Excitation inputs: The inputs (J and K for J-K flip-flops) applied to the memory elements that determine the next state on a clock transition. 📐 Formula: For a 3-bit up counter:

• J₂ = Q₁Q₀
• K₂ = Q₁Q₀
• J₁ = Q₀
• K₁ = Q₀
• J₀ = 1
• K₀ = 1

📌 Example: For the 3-bit up/down counter, when present state is 000 and X=0 (up), the next state is 001. The J-K inputs are J₂=0, K₂=x, J₁=0, K₁=x, J₀=1, K₀=x, causing Q₀ to toggle from 0 to 1 on the clock transition.

⭐ Key Takeaways

A student must remember that synchronous up/down counters use additional logic to control counting direction, with the 74HC190 IC providing a compact 4-bit implementation. Counter decoding uses logic gates to detect specific states, but glitches caused by propagation delays must be eliminated using the strobing method where decoder outputs are enabled only after glitches have settled. Practical applications like digital clocks and frequency counters rely on cascaded counters with accurate timing signals. The systematic design procedure for sequential circuits — state diagram, next-state table, flip-flop transition table, Karnaugh maps, logic expressions, and circuit implementation — is essential for designing counters with arbitrary counting sequences, as demonstrated with the 3-bit up/down counter.

🧠 Quick Revision Questions

1. What is the only difference between a synchronous up-counter and a synchronous down-counter circuit?
2. How does the UP/DOWN input control the counting direction in an up/down counter?
3. What are glitches in counter decoding, and how does the strobing method eliminate them?
4. Explain how a divide-by-60 counter is implemented using two 74HC160A decade counters.
5. List the six steps in the sequential circuit design procedure and the simplified Boolean expressions for J₂, K₂, J₁, K₁, J₀, and K₀ for a 3-bit up/down counter.

📘 Lecture 30 — DIGITAL CLOCK

📖 Overview: This lecture examines the complete design of a digital clock using cascaded counter circuits, including the divide-by-60 seconds/minutes counter and the 12-hour operation of the hours counter. It then introduces the design of a frequency counter for measuring unknown signal frequencies and transitions into the formal design methodology for Clocked Synchronous State Machines, including Mealy and Moore machine definitions.

🗂️ Topics Covered

The lecture covers the timing analysis of a divide-by-60 minutes/seconds counter including the operation of units and tens counters with RCO signals and clear logic. It describes the hours counter circuit configured as a decade counter with a J-K flip-flop and NAND gate logic to implement the 12-hour reset. It then presents a complete frequency counter circuit design, explaining how sampling intervals and crystal-controlled oscillators ensure accurate frequency measurement. Finally, it introduces the formal design procedure for Synchronous Counters and Clocked Synchronous State Machines, distinguishing between Mealy and Moore machines.

📝 Lecture Summary

Digital Clock

The timing diagram figure 30.1a shows the time interval t₆ to t₁₁ and t₁₉ to t₂₁. At time interval t₉ the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade counter. The RCO signal is set to logic 1 to indicate the terminal count. The RCO signal is connected to the ENP and ENT enable signals of the tens counter. At interval t₁₀ the tens counter is incremented by 1, the units counter recycles to 0000 (0) and the RCO signal is deactivated inhibiting the tens counter from incrementing. At interval t₁₉ the units counter once again reaches its terminal count activating the RCO signal and enabling the tens counter to increment its initial count 0001 to 0010. The counting sequence continues until the tens counter increments to 0101 (5) and the units counter recycles to 0000 and continues with the counting sequence on each positive clock transition.

The timing diagram fig 30.1b shows the timing sequence from interval t₅₆ to t₆₄. The unit counter reaches its terminal count at interval t₅₉. The output of the 3-input AND gate is set to logic high. The output of the AND gate is connected to the ENP and ENT enable inputs of the next counter, thus enabling the next counter. At interval t₆₀, on a positive clock transition the units counter recycles to 0000, the tens counter increments to 0110 (6) setting the output of the NAND gate to logic 0 and the next counter increments its count. The NAND gate output is connected to the asynchronous active low clear input of the tens counter which is asynchronously cleared to 0000.

🔑 Definition — Terminal Count: The maximum count value of a counter (e.g., 1001 for a decade counter), at which the RCO (Ripple Carry Output) signal is set to logic 1.

🔑 Definition — RCO (Ripple Carry Output): A signal that indicates when a counter has reached its terminal count, used to enable the next counter in a cascaded configuration.

📐 Formula: Divide-by-60 counter operation → Two cascaded decade counters (units and tens) where the tens counter counts from 0000 to 0101 (0-5), enabling a 3-input AND gate at the terminal count of both units and tens, while a NAND gate at count 0110 (6) asynchronously clears the tens counter.

Hours Counter

The hours unit counter circuit is configured as a decade counter, counting from 0000 to 1001 when it is enabled by the Minutes counter circuit. The NOT gate connected to the clock input of the J-K flip-flop allows the negative-edge triggered J-K flip-flop to trigger when the units counter is triggered to count from 0000 to 1001. The terminal count 1001 is detected by the NAND gate (1) at interval t₉ which sets the J input of the flip-flop to logic 1. The K input of the flip-flop is at Logic 0, therefore on a clock transition at interval t₁₀ the J–K flip-flop output Q is set to logic 1, the units counter recycles to 0000 resetting J input to logic 0.

The unit counter counts to 0001 and 0010 to represent hours 11 and 12 in interval t₁₁ and t₁₂ respectively. At interval t₁₂ as the unit counters count changes from 1011 (11) to 1100 (12), Q₁ output is set to logic 1, which sets the output of the NAND gate to logic 0 as the other input of the NAND is already at logic 1 (Q). The NAND gate sets the K input to logic 1 and setting the active-low LOAD signal to logic 0. At interval t₁₃, at the positive clock transition the unit counter is reloaded with the count 0001, the J-K flip-flop output toggles to logic 0 from logic 1. As the units counter is reloaded with count 0001, the K input is set to logic 0. At intervals t₁₄, t₁₅ and t₁₆ the hours unit counter increments the hours count by 1.

🔑 Definition — Hours Counter: A decade counter configured with a J-K flip-flop and NAND gates to implement the 12-hour clock cycle, reloading to 0001 (1) after reaching count 1100 (12).

💡 Why this matters: The hours counter design demonstrates how standard decade counters can be modified using feedback logic (NAND gates and J-K flip-flops) to implement non-standard counting sequences like the 12-hour format.

Frequency Counter

A frequency counter is used to measure the frequency of an input signal. The basis for the operation of a frequency counter is counting of the clock pulses in a predetermined time interval. The frequency of periodic signal is the number of cycles in a time period of one second. The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted, Figure 30.3.

In the circuit shown, the input signal with unknown frequency is applied at the AND gate input. The second input of the AND gate is connected to a signal which determines the sampling interval. The signal is set to logic high at interval t₁ to enable the AND gate allowing the input signal to be connected to the clock input of the counter circuit. The sampling interval signal is set to logic low at the end of the sampling interval t₂ to disable the AND gate and inhibit the counter from counting. Before the counter counts the clock pulses of the input signal it is reset by activating the Asynchronous input to clear the counter. At the end of the sampling interval the counter output is displayed on 7-segment displays.

The accuracy of the frequency counter depends on the duration of the timing sampling interval, which must be very accurate. Consider that during a sampling interval of 1 second 4573 clock pulses of the input signal are measured. Thus, the frequency of the unknown signal is 4573 Hz. If the same input signal is sampled using a 0.1 second sampling interval then 457.3 pulses are counted, which means that either 457 or 458 will be counted depending on the start of the sampling interval at t₁. Thus the frequency is determined to be either 4570 or 4580. Similarly, if the sampling interval is reduced to 0.01 seconds, the numbers of clock pulses measured are 45.73, which means that either 45 or 46 will be read indicating a frequency of 4500 or 4600.

Very accurate sampling intervals are implemented using cascaded counters which are connected to a very accurate timing signal generated by a crystal controlled oscillator (Astable multi-vibrator). The output timing signal of each cascade section is available at a switch which is used to select the appropriate timing signal for controlling the sampling interval. The output of the switch is connected to the clock input of a negative triggered J-K flip-flop, which divides the input signal by 2. Thus, when the 1 Hz sampling interval is selected, the signal at the output of the J-K flip-flop has a time period of 2 seconds. Figure 30.4.

The detailed circuit diagram and the timing diagram of the frequency counter are shown in figure 30.5. In the timing diagram the Sampling Interval pulse is obtained from the output of the J-K flip-flop shown in figure 30.4. The duration of the Sampling interval pulse can be selected through the switch. The sampling interval signal is connected to the input of the 3-input AND gate and the clock input of the second J-K flip-flop which toggles its output at each negative transition of the clock. When the output of the second flip-flop changes to logic 1 (interval t₁) it triggers the One-Shot which generates a short output pulse which clears the Counter circuit. At interval t₂ during the positive half of the sampling interval when the output of the second J-K flip-flop is high the 3-input AND gate is enabled and the input signal with unknown frequency is applied at the input of the counter, which counts the input signal pulses. At interval t₃ there is negative transition of the sampling signal, which triggers the second flip-flop changing its output to logic 0. Logic 0 output of the flip-flop disables the 3-input AND gate inhibiting the counter from counting. The pulses counted by the counter during interval t₂ to t₃ are directly displayed.

🔑 Definition — Frequency Counter: A circuit that measures the frequency of an unknown signal by counting clock pulses within a precise sampling interval, with frequency = (number of pulses counted) / (sampling interval duration).

📐 Formula: Frequency measurement accuracy → f = N/T, where N is the number of clock pulses counted and T is the sampling interval duration. Shorter sampling intervals reduce accuracy due to fractional pulse counting errors.

📌 Example: With a 1-second sampling interval, 4573 pulses are counted → frequency = 4573 Hz. With a 0.1-second interval, 457 or 458 pulses → frequency = 4570 or 4580 Hz (less accurate).

Design of Synchronous Counters

The counters that have been discussed are binary counters that count in a sequence either upwards or downwards. The count start and end sequence of a counter can also be set arbitrarily and the counter can then count up or down within the terminal count limits. Counters can also be designed that do not count in a sequence, instead they sequence through a set of predefined arbitrary values. Counters can also be implemented using D flip-flops instead of J-K flip-flops. No formal method of designing Counters has been discussed; however during the study of synchronous counters a general procedure was discussed which helps in the implementation of the counters. The procedure requires listing of the binary counting sequence and then determining the input condition for each flip-flop which promotes a change in their output state. The input conditions are dependent on the previous start outputs of the flip-flops and are implemented by using logic gates. The method does help in implementing counters but it is not a comprehensive method for the design and implementation of different types of counters.

🔑 Definition — Synchronous Counters: Binary counters that count in a predefined sequence (up or down) where all flip-flops share a common clock signal.

Clocked Synchronous State Machines

The Synchronous Counters are the simplest forms of Clocked Synchronous State Machines. State Machine is a generic name given to Sequential circuits. The Sequential circuits use a clock signal to change from one state to the other and all the flip-flops are connected to a single clock signal, therefore it is a Clocked Synchronous State Machine.

A general Sequential circuit consists of a combinational circuit and a memory element. The memory element is made of a set of n flip-flops all connected to a common clock. The n flip-flops store 2ⁿ states. The flip-flops change their current state to the next state on each clock transition. The next state is determined by the current state and the external input. The output of the State Machine is determined by the current state and external input. The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables. The present state of the memory is represented by state variables. The state variables and the inputs to the sequential circuit determine the sequential circuit output.

The Sequential circuit whose output depends on the current state and the input is known as Mealy Machine. Figure 30.6a. Sequential circuits whose output is determined by the current state only is known as Moore Machine. Figure 30.6b.

🔑 Definition — Clocked Synchronous State Machine: A sequential circuit where all flip-flops are connected to a single clock signal, and the next state is determined by the current state and external inputs.

🔑 Definition — Mealy Machine: A sequential circuit whose output depends on both the current state and the external input.

🔑 Definition — Moore Machine: A sequential circuit whose output depends only on the current state.

🔑 Definition — Excitation Variables: The inputs to the memory elements (flip-flops) that allow the memory to change its state on a clock transition.

Design Procedure

The design and implementation of Synchronous Counters follows an established set of steps and rules which start from defining the state diagram and end at the implementation of the State machine.

State Diagram

A sequential circuit (state machine) is described by a state diagram, which shows the sequence of states through which the sequential circuit progresses when it is clocked. The state diagram of a 3-bit Synchronous Up-Counter (sequential circuit) is shown in the figure 30.7, Figure 30.7.

🔑 Definition — State Diagram: A graphical representation showing the sequence of states a sequential circuit progresses through when clocked.

📌 Example: A 3-bit Up-Counter state diagram shows eight states (000 to 111) with transitions on each clock pulse, incrementing the binary count by 1.

⭐ Key Takeaways

The design of a digital clock requires careful cascading of decade counters using RCO signals and enable inputs, where the divide-by-60 seconds/minutes counter uses both 3-input AND gates for enabling the next stage and NAND gates for asynchronous clearing. The hours counter is a specialized design that uses a J-K flip-flop and NAND gate logic to detect counts 1001 (9) and 1100 (12), reloading to 0001 (1) to implement the 12-hour cycle. Frequency counters operate by counting unknown signal pulses within a precisely controlled sampling interval, where accuracy directly depends on the duration of the sampling interval — longer intervals yield greater precision. The formal design of sequential circuits introduces Clocked Synchronous State Machines, categorized as Mealy machines (output depends on current state and input) and Moore machines (output depends only on current state), with state diagrams providing the graphical foundation for the design procedure.

🧠 Quick Revision Questions

1. How does the RCO signal enable the tens counter in the divide-by-60 minutes/seconds counter when the units counter reaches its terminal count of 1001?
2. What logic circuit detects the hours count of 1100 (12) and how does it cause the units counter to reload to 0001?
3. Why does reducing the sampling interval in a frequency counter from 1 second to 0.1 seconds decrease measurement accuracy?
4. What is the fundamental difference between a Mealy Machine and a Moore Machine in terms of how the output is determined?
5. How does the 3-input AND gate and the J-K flip-flop in the detailed frequency counter circuit ensure the counter is cleared before each new measurement cycle?

📘 Lecture 31 — Lesson No. 31

📖 Overview: This lecture covers the complete process of designing synchronous sequential circuits, specifically a 3-bit up-counter, starting from the state diagram to the final circuit implementation. It demonstrates how to derive next-state tables, use flip-flop transition tables, apply Karnaugh maps for simplification, and implement the counter using both J-K and S-R flip-flops.

🗂️ Topics Covered

The lecture progresses through the sequential design process: starting with the Next-State Table definition, then the Flip-flop Transition Table for J-K and S-R flip-flops, followed by Karnaugh Map simplification for flip-flop input expressions, and finally the Sequential Circuit Implementation showing the counter circuit and its timing diagram using both J-K and S-R flip-flops.

📝 Lecture Summary

2. NEXT-STATE TABLE

Once the state diagram of the sequential circuit is defined, a Next-State Table is derived which lists each present state and the corresponding next state. The next state is the state to which the sequential circuit switches when a clock transition occurs.

🔑 Definition — Next-State Table: A table that lists all possible present states (Q₂Q₁Q₀) and the corresponding next state (Q₂⁺Q₁⁺Q₀⁺) after a clock transition.

📌 Example: Table 31.1 shows the Next-State Table for a 3-bit up-counter. For present state 000, the next state is 001. For present state 111, the next state is 000 (it wraps around).

3. Flip-flop Transition Table

The Memory element of the Sequential circuit is implemented using flip-flops. The number of flip-flops used is determined by the total number of states. The Flip-flop transition table lists all possible flip-flop input combinations which allow the present state to change to the next state on a clock transition.

🔑 Definition — J-K flip-flop Transition Table (Table 31.2):

• J=0, K=x (don't care) → Qₜ=0 becomes Qₜ₊₁=0
• J=1, K=x → Qₜ=0 becomes Qₜ₊₁=1
• J=x, K=1 → Qₜ=1 becomes Qₜ₊₁=0
• J=x, K=0 → Qₜ=1 becomes Qₜ₊₁=1

💡 Why this matters: The J-K flip-flop has "don't care" conditions that simplify logic expressions, making it more flexible than S-R or D flip-flops.

4. Karnaugh Maps

For each state variable shown in the Next-State table, the change from present state to next state on a clock transition depends upon the J-K inputs. The table is completed using the information in the Next-State table and the J-K flip-flop transition table.

🔑 Definition — Karnaugh Map: A graphical method for simplifying Boolean expressions, where adjacent cells differ by only one variable.

📐 Formulas (from Table 31.4):

• J₂ = Q₁Q₀
• K₂ = Q₁Q₀
• J₁ = Q₀
• K₁ = Q₀
• J₀ = 1
• K₀ = 1

📌 Example: For this 3-bit up-counter, J₀ and K₀ are always 1, meaning the least significant flip-flop toggles on every clock pulse. J₁ and K₁ are tied to Q₀, so the second flip-flop toggles only when Q₀=1.

5. Logic expressions for Flip-flop Inputs

Simplified expressions for J₂-K₂, J₁-K₁, and J₀-K₀ are directly obtained from the Karnaugh maps. These expressions represent the minimal logic needed to drive each flip-flop.

6. Sequential Circuit Implementation

The Boolean expressions obtained are implemented using logic gates to create the sequential circuit.

📌 Example: Figure 31.1 shows the implementation of the 3-bit synchronous up-counter using J-K flip-flops. Each flip-flop has its J and K inputs connected according to the simplified expressions, and all share a common clock (CLK) signal.

S-R flip-flop based Implementation

To implement the counter using S-R flip-flops instead of J-K flip-flops, the S-R transition table is used. The S-R flip-flop does not allow S and R inputs to be set to logic 1 and 1 respectively (invalid state).

🔑 Definition — S-R flip-flop Transition Table (Table 31.5):

• S=0, R=x → Qₜ=0 becomes Qₜ₊₁=0
• S=1, R=0 → Qₜ=0 becomes Qₜ₊₁=1
• S=0, R=1 → Qₜ=1 becomes Qₜ₊₁=0
• S=x, R=0 → Qₜ=1 becomes Qₜ₊₁=1

📐 Formulas (from Table 31.7):

• S₂ = Q₂Q₁Q₀
• R₂ = Q₂'Q₁Q₀
• S₁ = Q₁'Q₀
• R₁ = Q₁Q₀
• S₀ = Q₀'
• R₀ = Q₀

📌 Example: In the S-R flip-flop implementation (Figure 31.2a), the first flip-flop's S and R inputs are cross-connected to its Q and Q' outputs (S₀ = Q₀', R₀ = Q₀). At interval t₁, Q₀=0, so R=0 and S=1, setting the flip-flop to logic 1 on the clock transition. At t₂, Q₀=1, so S=0 and R=1, resetting it to 0. The second flip-flop (FF2) toggles when Q₀=1, and the third (FF3) toggles when both Q₀ and Q₁ are 1.

⭐ Key Takeaways

The sequential circuit design process follows six systematic steps: defining the state diagram, creating the next-state table, selecting flip-flop type and using its transition table, deriving Karnaugh maps for flip-flop inputs, simplifying to get Boolean expressions, and implementing the circuit with logic gates. For a 3-bit up-counter, J-K flip-flops yield simpler expressions (J₀=K₀=1, J₁=K₁=Q₀, J₂=K₂=Q₁Q₀) compared to S-R flip-flops (S₂=Q₂Q₁Q₀, R₂=Q₂'Q₁Q₀, etc.), demonstrating the design trade-offs. The "don't care" conditions in J-K flip-flops allow for more compact circuits, making them preferred for counter implementations.

🧠 Quick Revision Questions

1. What is the purpose of a Next-State Table in sequential circuit design, and what information does it contain?
2. Why does the J-K flip-flop often produce simpler logic expressions than the S-R flip-flop for the same sequential circuit?
3. For the 3-bit up-counter using J-K flip-flops, what are the simplified expressions for J₂ and K₂?
4. What is the invalid input combination for an S-R flip-flop, and why is it invalid?
5. In the S-R flip-flop implementation of the 3-bit counter, why does the second flip-flop only change state when Q₀=1?

📘 Lecture 32 — D FLIP-FLOP BASED IMPLEMENTATION

📖 Overview: This lecture focuses on implementing sequential circuits using D flip-flops instead of J-K flip-flops, using D transition tables and Karnaugh maps to derive simplified input expressions. It also covers the design of a 3-bit Up/Down Synchronous Counter using J-K flip-flops, and introduces the concept of state reduction to eliminate equivalent states for simpler circuit design. Understanding these methods is crucial for optimizing digital systems.

🗂️ Topics Covered

The lecture covers the D flip-flop transition table and its use in implementing a 3-bit synchronous counter, deriving simplified logic expressions from Karnaugh maps for D inputs, and analyzing the resulting timing diagram. It then transitions to implementing a 3-bit Up/Down counter using J-K flip-flops, including state diagrams, next-state tables, and Karnaugh maps for J-K inputs. Finally, it introduces state reduction by identifying and eliminating equivalent states to minimize the number of flip-flops and simplify the circuit.

📝 Lecture Summary

Flip-Flop Transition Table

To implement a counter using D flip-flops, the D transition table is used. The D flip-flop has a single input, and the output follows the input. The D flip-flop transition table shows that when the input D is 1, the next output (Q_{t+1}) is 1; when D is 0, the next output is 0.

🔑 Definition — D Flip-Flop Transition Table: A table showing the relationship between the D input and the next state output. For (Q_t \rightarrow Q_{t+1}), D = (Q_{t+1}).

Karnaugh Maps

The D input table is derived from the present state and next state of a 3-bit counter. The Karnaugh maps for the input expressions D₂, D₁, and D₀ are created from this table.

Table 32.2 D flip-flop input table

Logic expressions for Flip-flop Inputs

Simplified expressions for D₂, D₁, and D₀ are obtained from the Karnaugh maps.

📐 Formula:

• (D_2 = Q_2 \oplus Q_1 Q_0)
• (D_1 = Q_0 \oplus Q_1)
• (D_0 = Q_0)

💡 Why this matters: These simplified expressions are directly used to design the combinational logic for the counter’s next state, making the circuit simpler and more efficient.

Sequential Circuit Implementation

The D flip-flop implementation is described. The first D flip-flop toggles at each clock transition. The input to the second flip-flop is determined by (D_1 = Q_0 \oplus Q_1). The input to the third flip-flop is determined by (D_2 = Q_2 \oplus Q_1 Q_0).

📌 Example: For the second flip-flop, at intervals t₁, t₄, t₅, and t₈, the input D₁ is at logic 0, setting output Q₁ to logic 0. At intervals t₂, t₃, t₆, and t₇, the input D₁ is at logic 1, setting output Q₁ to logic 1. For the third flip-flop, at intervals t₁, t₂, t₃, and t₈, D₂ input is at logic 0, setting Q₂ to 0. At intervals t₄, t₅, t₆, and t₇, D₂ input is at logic 1, setting Q₂ to logic 1.

Implementing a 3-bit Up/Down Counter

A 3-bit Up/Down Synchronous Counter is implemented using J-K flip-flops. The counter counts up when input X = 0 and counts down when X = 1.

7. State Diagram

The state diagram of a 3-bit Up/Down Synchronous Counter is shown. X=0 and X=1 indicate the counting direction.

8. Next-State Table

The next-state table shows the next state for both X=0 (up counting) and X=1 (down counting).

Table 32.4 Next-State Table for a 3-bit Up-Counter

9. Flip-flop Transition Table

The flip-flop transition table is based on the J-K flip-flop. It shows the required J and K inputs for all possible output transitions.

Table 32.5 J-K flip-flop Transition table

10. Karnaugh Maps

The J-K flip-flop inputs for both X=0 and X=1 are mapped to 4-Variable Karnaugh maps to derive simplified expressions.

11. Logic expressions for Flip-flop Inputs

Simplified expressions for J₂-K₂, J₁-K₁, and J₀-K₀ are obtained from the Karnaugh maps.

📐 Formula:

• (J_0 = 1, K_0 = 1)
• (J_1 = Q_0 \overline{X} + \overline{Q_0} X, K_1 = \overline{Q_0}\overline{X} + Q_0 X)
• (J_2 = Q_1 Q_0 \overline{X} + \overline{Q_1} \overline{Q_0} X, K_2 = \overline{Q_1} Q_0 \overline{X} + Q_1 \overline{Q_0} X)

12. Sequential Circuit Implementation

The Boolean expressions are implemented using logic gates to create the full sequential circuit.

State Reduction

A state diagram shows the sequence of current and next states. Two states are considered equivalent if, for the same set of inputs, they change to the same next state (or equivalent next states) and give identical outputs. If equivalent states exist, one is removed, leading to fewer flip-flops and a simpler circuit. Reduction in the number of states is possible if only the input-output relationship is of interest.

🔑 Definition — Equivalent States: Two states are equivalent if, for every possible input, they transition to the same next state (or equivalent next states) and produce the same output.

📌 Example: Consider the state sequence a, b, c, f, d, d, e, g, e, g, d, e, a, f, d, e, a. In the next-state table, state ‘f’ and state ‘g’ are equivalent as for each input set they transition to ‘d’ and ‘e’ and have identical outputs. State ‘g’ is eliminated and replaced by ‘f’. Further, state ‘c’ and state ‘e’ are found to be equivalent and state ‘e’ is eliminated and replaced by ‘c’. This reduces the number of unique states from seven to five.

Table 32.9c Final simplified Next State table

💡 Why this matters: Eliminating equivalent states reduces the number of required flip-flops. In this example, reducing from seven to five states did not change the number of flip-flops (still three), but if the number of states were reduced to four, only two flip-flops would be needed, resulting in a simpler and cheaper circuit.

⭐ Key Takeaways

This lecture is critical for understanding how to implement counters using different flip-flop types and how to optimize sequential circuits. Key points include mastering the D flip-flop transition table and using Karnaugh maps to derive simplified input expressions for a 3-bit counter. For the up/down counter, you must be able to create next-state tables for both counting directions and derive J-K input expressions from 4-variable Karnaugh maps. Finally, the concept of state reduction is essential; you must be able to identify equivalent states in a state diagram, eliminate them, and understand how this process can minimize the number of flip-flops and simplify the overall circuit design.

🧠 Quick Revision Questions

1. According to the D flip-flop transition table, what should the D input be to change the output from 0 to 1?
2. What are the simplified Boolean expressions for D₂, D₁, and D₀ for the 3-bit D flip-flop based synchronous counter?
3. In the 3-bit Up/Down counter, what is the next state for the present state 101 when X=1 (counting down)?
4. What is the formula for J₁ in the 3-bit Up/Down counter, and what does the variable X represent?
5. In the state reduction example, which two pairs of states were identified as equivalent and subsequently reduced?

📘 Lecture 33 — State Assignment

📖 Overview: This lecture explores the process of assigning binary codes to states in sequential circuits to minimize the complexity of combinational logic. It demonstrates with detailed examples that different state assignments yield different Boolean expressions, and provides guidelines for selecting optimal assignments. The lecture also presents Moore and Mealy machine implementations for the same state diagram.

🗂️ Topics Covered

The lecture covers state assignment concepts and guidelines for sequential circuits, including three different state assignments for a six-state machine and their resulting flip-flop input tables and Karnaugh maps. It then presents a complete Moore Machine design from state diagram through J-K flip-flop implementation with timing diagrams, followed by a parallel Mealy Machine design showing the differences in state diagram, next-state tables, and output implementation.

📝 Lecture Summary

State Assignment

Each state in a sequential circuit is identified by a unique combination of binary bits. Unless the output is directly taken from flip-flop outputs (as in counters), states can be selected to allow minimum bit changes when changing from one state to another. Keeping bit changes to a minimum results in simpler combinational circuits that determine the next state.

🔑 Definition — State Assignment: The process of assigning unique binary codes to each state in a sequential circuit to minimize the complexity of the next-state and output logic.

Three possible state assignments for states a, b, c, d and f are shown:

Table 33.1 Three possible state assignments

For State Assignment 1, the D flip-flop input table (Table 33.2a) and Karnaugh maps (Table 33.2b) yield:

• D₂ = Q₂Q₁Q₀x + Q₁Q₀X
• D₁ = Q₂ + Q₀X + Q₁Q₀
• D₀ = Q₂Q₀X + Q₁Q₀X + Q₁Q₀X + Q₂Q₁Q₀X

For State Assignment 2, (Table 33.3a, 33.3b):

• D₂ = Q₂Q₁x + Q₁Q₀X + Q₂Q₁X + Q₂Q₁X
• D₁ = Q₂Q₀ + Q₁Q₀ + Q₁X + Q₁X
• D₀ = Q₂Q₁X + Q₁Q₀X + Q₁Q₀X

For State Assignment 3, (Table 33.4a, 33.4b):

• D₂ = Q₁Q₀x + Q₁Q₀X
• D₁ = Q₀x + Q₀X + Q₁Q₀
• D₀ = Q₂Q₁Q₀x + Q₂X + Q₁Q₀ + Q₁X

The third State Assignment is shown to have simpler input Boolean expressions leading to a simpler combinational circuit.

Guidelines for State Assignment:

• Choose an initial coded state into which the state machine can easily be forced to reset (000 or 111)
• Minimize the State Variables that change on each transition
• Maximize the number of state variables that don't change in a group of related states
• If there are unused states, choose the best state variable combinations to achieve the first three goals

Moore Machine State Diagram

The state diagram of a Moore Machine is shown (Figure 33.1). The Clocked Synchronous Sequential Circuit has six states. On each clock transition the machine sequences through the states 011, 111, 001, 010, 100 and 110. The outputs of the flip-flops represent the sequential circuit output.

Next-State Table (Moore Machine)

The Next-State table (Table 33.5) is derived from the State diagram:

Karnaugh Maps (Moore Machine)

The J-K flip-flop input table (Table 33.6) uses the J-K flip-flop transition table to determine inputs. The Karnaugh maps (Table 33.7a-c) yield:

• J₂ = Q₁, K₂ = Q₁
• J₁ = 1, K₁ = Q₂Q₀ + Q₂Q₀
• J₀ = Q₂Q₁, K₀ = Q₁

Implementation (Moore Machine)

The circuit and timing diagram (Figure 33.2) shows the State Machine. The sequential circuit is assumed to be reset to state 011. At interval t₁, J-K input of the first flip-flop is set at 0 and 0 respectively; therefore at the clock transition the output of the first flip-flop remains unchanged. The J input of the second flip-flop is permanently connected to logic 1, the K input is set at logic 0, therefore the output of the second flip-flop is set to logic 1 at the clock transition t₁. The J-K input of the third flip-flop is set to logic 1, at clock transition t₁ the output of the flip-flop changes to logic 1.

💡 Why this matters: The Moore Machine outputs depend only on the present state (flip-flop outputs), making them stable between clock transitions but requiring more states for sequential problems.

Mealy Machine State Diagram

The sequential circuit represented earlier as a Moore Machine is described as a Mealy Machine (Figure 33.3). The output of a Mealy machine depends upon the present state at the inputs. The state diagram shows six states. When the input is 1, the machine switches from its present state to the next. If the input is 0, the machine remains in its present state.

Next-State Table (Mealy Machine)

The Next-State table (Table 33.8) shows present state, next state for X=0 and X=1, and outputs for each input condition:

State Assignments (Mealy Machine)

Based on guidelines, states are assigned keeping bit changes to minimum (Table 33.9):

Karnaugh Maps (Mealy Machine)

The J-K flip-flop input tables (Table 33.10a-b) and Karnaugh maps (Table 33.11a-d) yield:

• J₂ = Q₁Q₀X, K₂ = Q₁X
• J₁ = Q₀X, K₁ = Q₂X
• J₀ = Q₂Q₁X, K₀ = Q₁X
• O₂ = Q₂X + Q₂Q₁ + Q₂Q₀X + Q₁Q₀X
• O₁ = Q₁Q₀X + Q₂Q₀X + Q₂X + Q₁Q₀ + Q₁X
• O₀ = Q₁X + Q₂Q₁ + Q₀X

Implementation (Mealy Machine)

The machine is assumed to be reset to state 'a' 000. At interval t₁, J-K inputs of the first flip-flop are set at logic 1 and 0 respectively, therefore at the clock transition the output of the first flip-flop switches from 0 to 1. The J-K inputs of the second flip-flop are set at logic 0 and 0 respectively, thus the output state of the second flip-flop remains unchanged. The J-K inputs of the third flip-flop are set to logic 0 and 1 respectively, thus at clock transition t₁ the flip-flop is reset to logic 0.

At interval t₁, before the clock transition, Q₀, Q₁ and Q₂ outputs are set at logic 0, 0 and 0 respectively. When the X input is logic 0, the output of Boolean expressions for O₂, O₁ and O₀ is 0, 1 and 1 respectively. At the clock transition t₁ when the X input is set to 1, the outputs O₂, O₁ and O₀ are set to 1, 1 and 1.

💡 Why this matters: The Mealy Machine outputs depend on both present state AND inputs, often requiring fewer states than a Moore machine for the same task, but outputs can change asynchronously with input changes.

⭐ Key Takeaways

State assignment is a critical design step that directly impacts the complexity of combinational logic in sequential circuits, with different assignments producing drastically different Boolean expressions. The third state assignment demonstrated simpler logic than the other two, following guidelines of minimizing bit changes between states and maximizing unchanged state variables. Both Moore and Mealy machines can implement the same state diagram, but Moore outputs depend only on the present state while Mealy outputs depend on both present state and inputs, making Mealy potentially more compact but with timing differences. J-K flip-flop implementations for both machines were fully derived from state diagrams through next-state tables and Karnaugh maps, showing the complete design process from specification to circuit implementation.

🧠 Quick Revision Questions

1. What are the four guidelines for selecting an optimal state assignment in sequential circuits?
2. How does the third state assignment produce simpler Boolean expressions compared to the first two?
3. What is the key difference between Moore and Mealy machine outputs in terms of what they depend on?
4. In the Moore machine example, what is the sequence of states (starting from 011) and what are the J-K input expressions for each flip-flop?
5. For the Mealy machine, why does the output change when input X changes even before the clock transition occurs?

📘 Lecture 34 — SHIFT REGISTERS

📖 Overview: This lecture covers the storage and shifting of binary data using shift registers built from multiple flip-flops. It explains different shift operations and register configurations, including serial and parallel data movement, bidirectional shifting, and specialized counter circuits like the Johnson and Ring counters, which are fundamental in digital systems for data manipulation and timing.

🗂️ Topics Covered

This lecture covers seven shift operations (Serial In/Shift Right/Serial Out, Serial In/Shift Left/Serial Out, Serial In/Parallel Out, Parallel In/Serial Out, and Parallel In/Parallel Out), bidirectional shift registers, rotate operations (right and left), and shift register counters including the Johnson Counter and Ring Counter with their specific circuit configurations and state sequences.

📝 Lecture Summary

Lesson No. 34 - SHIFT REGISTERS

A flip-flop stores a single binary bit. Multiple bits are stored using multiple flip-flops with their clock inputs connected together. A register performs two basic functions: it stores data and it moves or shifts data. The shifting of data involves moving bits from one flip-flop to another within the register or moving data in and out. The shift operation is carried out by applying clock signals.

1. Serial In/Shift Right/Serial Out Operation

Data is shifted in the right-hand direction one bit at a time with each transition of the clock signal. Data enters the shift register serially from the left-hand side. After four clock transitions, the 4-bit register has 4 bits of data. Data is shifted out serially one bit at a time from the right-hand side if clock signals are continuously applied. Thus, after 8 clock signals, the 4-bit data is completely shifted out.

🔑 Definition — Serial In/Shift Right/Serial Out: A shift register operation where data enters one bit at a time from the left and exits one bit at a time from the right.

2. Serial In/Shift Left/Serial Out Operation

Data is shifted in the left-hand direction one bit at a time with each transition of the clock signal. Data enters the shift register serially from the right-hand side. After four clock transitions, the 4-bit register has 4 bits of data. Data is shifted out serially one bit at a time from the left-hand side. Thus, after 8 clock signals, the 4-bit data is completely shifted out.

A Serial Shift register can be implemented using any type of flip-flops, such as D flip-flops. At each clock transition, 1 bit of serial data is shifted in and 1 bit of serial data is shifted out. As data is shifted out, a logic 0 value is usually shifted in to fill the vacant bits.

Bidirectional Shift Registers allow data to be shifted left or right. This is configured by setting the RIGHT / LEFT signal to logic high or low. When configured to shift right, AND gates marked 1 are enabled, connecting the input of the first flip-flop to the Serial Input, and the inputs of the next three flip-flops to the Q outputs of the previous flip-flops. Serial data is shifted out through output Q₃. When configured to shift left, AND gates marked 2 are enabled, connecting Q outputs of the right-hand flip-flop to the D input of the left-hand flip-flop. Serial data out is available through the Q₀ output.

🔑 Definition — Bidirectional Shift Register: A shift register that can be configured to shift data either left or right based on a control signal.

3. Serial In/Parallel Out Operation

Data is shifted in one bit at a time with each clock transition. After four clock transitions, the 4-bit register has 4 bits of data. The data is shifted out in parallel by the application of a single clock signal. The shift register has 4 parallel outputs.

The 74HC164 is an MSI 8-bit Serial In/Parallel Out Shift Register. It has 8 parallel outputs, an Asynchronous Active-low CLR input, and is triggered on the positive clock transition. Serial data is applied through inputs A and B, which are internally connected through an internal NAND gate. Setting one input to logic high enables the shift operation. The register is cleared asynchronously by activating the active-low CLR input.

🔑 Definition — Serial In/Parallel Out: A shift register operation where data enters one bit at a time and is available simultaneously on all outputs after the register is full.

4. Parallel In/Serial Out Operation

The register has parallel inputs. Data bits are loaded into the register in parallel by activating a load signal. Data is shifted out serially by application of clock signals. In a 4-bit shift register, after 4 clock signals, the 4-bit data is completely shifted out.

Data is initially loaded in Parallel by setting the SHIFT / LOAD input to logic low, enabling AND gates marked 2 to apply data to the D inputs of the flip-flops. On a positive clock transition, the data is latched. To shift, SHIFT / LOAD is set to logic high, enabling AND gates marked 1, which connect the Q output of each flip-flop to the D input of the next flip-flop.

The 74HC165 is an 8-bit Parallel In/Serial Out register that can also work as a Serial In/Serial Out register. Parallel data is loaded asynchronously using the Asynchronous Set/Clear Inputs. The clock signal is enabled by setting the CLK INH signal to logic low.

🔑 Definition — Parallel In/Serial Out: A shift register operation where all data bits are loaded simultaneously and then shifted out one bit at a time.

5. Parallel In/Parallel Out Operation

The register has parallel inputs and parallel outputs. Data is entered in parallel by applying a single clock pulse. Data is latched by the flip-flops on the clock transition and is available in parallel form at the flip-flop outputs. This register stores parallel data and usually does not allow any shift operations.

The 74HC195 is a 4-bit Parallel In/Parallel Out Register. It also has a Serial In input, allowing it to be used as a Serial In/Parallel Out or Serial In/Serial Out register. The J and K inputs are used to input data serially. The SH/ LD pin is used to load parallel data and allow shift operations.

The 74HC194 is a 4-bit Bidirectional Shift register that shifts data left and right and has both Parallel and Serial input/output capability. The S₀ and S₁ inputs control the operation. When both are at logic high, the register loads parallel data. When S₀ is high, shift right operation is carried out with serial data through the SR SER input. When S₁ is high, shift left operation is carried out with serial data through the SL SER input. When both are logic low, the register is inhibited.

🔑 Definition — Universal Shift Register: A shift register that can perform multiple operations including parallel load, shift left, shift right, and hold, controlled by mode select inputs.

6. Rotate Right Operation

The serial output of the register is connected to the serial input of the register. By applying clock pulses, data is shifted right. The data shifted out of the serial out pin at the right-hand side is re-circulated back into the shift register input at the left-hand side. Thus, the data is rotated right within the register.

7. Rotate Left Operation

The serial output of the register is connected to the serial input of the register. By applying clock pulses, data is shifted left. The data shifted out of the serial out pin at the left-hand side is re-circulated back into the shift register input at the right-hand side. Thus, the data is rotated left within the register.

Shift Register Counters

Shift register counters are shift registers connected to perform rotate left and rotate right operations. When data is rotated through a register counter, a specific sequence of states is repeated. Two commonly used register counters are the Johnson Counter and the Ring Counter.

1. Johnson Counter

In a Johnson counter, the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop. The sequence of states implemented by an n-bit Johnson counter is 2n. A 4-bit Johnson counter sequences through 8 states.

📐 Formula: Number of states = 2n for an n-bit Johnson counter

📌 Example: For a 4-bit Johnson counter, the sequence is: 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001

2. Ring Counter

The Ring Counter is similar to the Johnson counter, except that the Q output of the last flip-flop is connected to the data input of the first flip-flop. All flip-flops are cleared to logic low except for the first flip-flop, which is preset to logic high. After initialization, the logic high is shifted right at each clock transition. With a Ring Counter, no decoding gates are required because each state has a unique output.

📌 Example: For a 4-bit Ring Counter, the sequence is: 1000 → 0100 → 0010 → 0001

⭐ Key Takeaways

A shift register is a fundamental digital circuit that stores and moves binary data, with operations classified by how data enters (serial or parallel) and exits (serial or parallel). Bidirectional shift registers like the 74HC194 allow data movement in both directions using control signals, while universal shift registers can perform multiple operations including parallel load, shift left, shift right, and hold. Rotate operations recirculate data by connecting output back to input, forming the basis for shift register counters. The Johnson counter produces 2n states and the Ring counter produces n states, each following a distinct state sequence that is critical for understanding timing and sequencing in digital systems.

🧠 Quick Revision Questions

1. How many clock transitions are required to completely shift in and shift out a 4-bit word using a Serial In/Serial Out shift register?
2. What is the difference between a Johnson counter and a Ring counter in terms of how the output of the last flip-flop is connected to the input of the first flip-flop?
3. In the 74HC164 8-bit Serial In/Parallel Out shift register, what is the function of the two inputs A and B?
4. How does the SHIFT/LOAD signal control the operation of a Parallel In/Serial Out shift register?
5. What is the state sequence for a 4-bit Johnson counter and how many states does it have?

📘 Lecture 35 — Applications of Shift Registers

📖 Overview: This lecture examines practical applications of shift registers, including serial-to-parallel conversion for asynchronous data transmission and keyboard encoding. It also introduces programmable sequential logic using PLD devices, specifically how to configure GAL22V10 devices for registered modes to implement shift registers and registers in hardware description languages like ABEL.

🗂️ Topics Covered

The lecture covers serial-to-parallel converters using shift registers for asynchronous serial data transmission with start and stop bits, keyboard encoder circuits using ring counters for row-column scanning, programmable sequential logic using PLD devices in registered mode, software mode specification using ISTYPE statements and dot extensions in ABEL, and three detailed examples: an 8-bit parallel I/O register with inverted outputs, an 8-bit serial in/parallel out shift register, and a 4-bit parallel in/serial out shift register.

📝 Lecture Summary

1. Serial-to-Parallel Converter

In Asynchronous Serial data transmission, an 8-bit character is transmitted with additional start and stop bits. A start bit (logic low) precedes the character to indicate data is coming, and stop bits (two logic high bits) follow to mark the end and return the line to idle. A total of 11 bits are transmitted per character: 1 start bit, 8 data bits, and 2 stop bits. The serial-to-parallel converter uses a J-K flip-flop triggered by the start bit, which enables a clock generator. The clock drives a Serial In/Parallel Out shift register and an 8-bit counter. When the counter reaches terminal count 111, it triggers a One-Shot that loads parallel data into a Parallel In/Parallel Out register and resets the system.

🔑 Definition — Asynchronous Serial Data Transmission: A method where data is sent one bit at a time without a shared clock, using start and stop bits to frame each character.

📌 Example: Transmitting character "A" (binary 01000001) requires the sequence: 0 (start), 01000001 (data), 1, 1 (stop) = 11 bits total.

💡 Why this matters: The start/stop bit framing allows receivers to synchronize with incoming data without needing a separate clock line, which is essential for UART communication in computers and microcontrollers.

2. Keyboard Encoder

A keyboard encoder regularly scans keys organized in rows and columns using a shift register based ring counter. The ring counter sequences through a bit pattern with all 1's and a single 0, selecting one row at a time by setting it to logic 0. When a key is pressed, the corresponding column also becomes logic 0. Row and column encoders encode the position. A NAND gate detects the column going low and triggers two One-Shots: the first inhibits the clock to the ring counter, and the second sends a pulse to the Key Code Register to store the 3-bit row and 3-bit column key ID.

🔑 Definition — Ring Counter: A shift register configured to circulate a single 0 (or 1) pattern, used for sequential selection in scanning applications.

💡 Why this matters: This scanning method reduces the number of connections needed for keyboards with many keys compared to direct encoding, making it practical for full-size computer keyboards.

Programmable Sequential Logic

PLD devices can implement sequential circuits by using the AND-OR array for excitation inputs and a flip-flop in each OLMC (Output Logic Macro Cell) module as the memory element. The present state output feeds back to the AND array. The output is obtained from a tri-state buffer connected to the PLD output pin.

The Registered Mode

In the Registered Mode, the OLMC is configured by setting MUX select inputs S1 and S0 to 01 or 00. With S1=0 and S0=1, the Q output of the D flip-flop is routed through the MUX to the tri-state buffer. Feedback to the AND gate array comes from the Q output, not the tri-state buffer output. Setting S1=0 and S0=0 connects the Q output (inverted) to the output while feedback remains from Q.

Software Mode Specification

The ISTYPE statement in ABEL declares whether an output is 'Registered' or 'Combinational'. The dot extension .CLK indicates a clocked flip-flop. Assignment operators := and :> indicate registered outputs, while = indicates combinational outputs.

🔑 Definition — ISTYPE: An ABEL declaration statement specifying the output mode of a PLD pin as 'reg' (registered), 'com' (combinational), 'reg.buffer' (active-high registered), or 'reg.invert' (active-low registered).

📐 Formula: X := D; → "X gets the value of D on the clock transition" 📐 Formula: X.CLK = Clock; → "X is clocked by the signal named Clock"

Example1: Parallel Input/Parallel Output 8-bit Register with inverted outputs

An 8-bit D flip-flop based register with inverted outputs using GAL22V10:

Clock, D0..D7 PIN 1, 2, 3, 4, 5, 6, 7, 8, 9;
Q0..Q7 PIN 22, 21, 20, 19, 18, 17, 16, 15 ISTYPE 'reg.invert';
[Q0..Q7] := [D0..D7];
[Q0..Q7].CLK = Clock;

Example2: 8-bit Serial In/Parallel Out Shift Register

ABEL implementation using GAL22V10 with Clear (asynchronous reset) and Enable controls:

Q0 := Data & Enable;
[Q1..Q7] := [Q0..Q6];
[Q0..Q7].CLK = Clock;
[Q0..Q7].AR = !Clear;

The test vectors verify shifting behavior: with Enable=0, no shift occurs; with Enable=1, data shifts in one bit per clock cycle.

🔑 Definition — Asynchronous Reset (AR): A control input that immediately clears a flip-flop regardless of the clock signal, specified in ABEL using the .AR dot extension.

📌 Example: The test vector [.c., 1, 1, 1] -> [1, 0, 0, 0, 0, 0, 0, 0] shows shifting in a '1' when Clock transitions, Clear=1, Data=1, Enable=1.

Example3: 4-bit Parallel In/Serial Out Shift Register

ABEL implementation with SHLD (Shift/Load) control:

Q0 := D0;
Q1 := Q0 & SHLD # D1 & !SHLD;
Q2 := Q1 & SHLD # D2 & !SHLD;
Q3 := Q2 & SHLD # D3 & !SHLD;
[Q0..Q3].CLK = Clock;
[Q0..Q3].AR = !Clear;

When SHLD=0, parallel data D0-D3 is loaded. When SHLD=1, data shifts right.

📌 Example: With SHLD=0 (load), D0=0, D1=1, D2=0, D3=1 → Q3 becomes 1 (the MSB loaded). With SHLD=1 (shift), the register shifts right on each clock.

⭐ Key Takeaways

The shift register's primary application is converting between parallel and serial data formats, essential for efficient data transmission. Asynchronous serial communication uses start and stop bits (11 bits total per character) for framing, and shift register based converters replace the more complex multiplexer/demultiplexer combinations. Keyboard encoders use ring counters and row-column scanning to detect key presses, encoding position as row and column codes. PLD devices in registered mode can implement sequential circuits like registers and shift registers, configured using ABEL with ISTYPE statements, dot extensions (.CLK, .AR), and assignment operators (:= for registered, = for combinational). The SHLD (Shift/Load) control distinguishes between parallel load and serial shift operations in shift register implementations.

🧠 Quick Revision Questions

1. In asynchronous serial transmission, how many total bits are transmitted per 8-bit character, and what are their functions?
2. How does the keyboard encoder circuit detect a key press using the ring counter and column NAND gate?
3. What is the difference between the Registered Mode and Combinational Mode in a PLD's OLMC?
4. In ABEL, what do the assignment operators := and = indicate, and what does the dot extension .CLK specify?
5. For the 4-bit parallel in/serial out shift register example, explain how the SHLD signal controls whether data is loaded in parallel or shifted serially.

📘 Lecture 36 — EXAMPLE 4: 3-BIT UP/DOWN COUNTER

📖 Overview: This lecture demonstrates the complete design process of a 3-bit Up/Down counter using D flip-flops, including Karnaugh map simplification, ABEL Hardware Description Language implementations using equations, truth tables, and state diagrams. It concludes with a comprehensive elevator control system design example that applies sequential state machine principles to a real-world application.

🗂️ Topics Covered

The lecture covers the D flip-flop input table and Karnaugh map simplification for a 3-bit Up/Down counter, ABEL implementation using Boolean equations with clock and clear definitions, test vector verification, alternative ABEL specifications using truth tables and state diagrams with IF-THEN-ELSE and GOTO statements, and a detailed elevator control system design including state definition, state diagram, state tables, and input latch requirements.

📝 Lecture Summary

Example 4: 3-BIT UP/DOWN COUNTER

The 3-bit Up/Down Counter previously implemented using J-K flip-flops is now implemented using D flip-flops by mapping present state and next state information into a D Input table. The simplified Boolean expressions derived from Karnaugh maps are used to implement the circuit.

For X=0 (up counting), the present state transitions follow: 000→001→010→011→100→101→110→111→000. For X=1 (down counting), the sequence reverses: 000→111→110→101→100→011→010→001→000.

Table 36.1a shows the D flip-flop input table for X=0, where D₂, D₁, D₀ represent the required D inputs to achieve the next state. Table 36.1b shows the corresponding table for X=1.

From the Karnaugh maps, the simplified Boolean expressions are derived:

D₂ = Q₂'Q₁'Q₀'X + Q₂'Q₁Q₀X' + Q₂Q₀'X' + Q₂Q₁X + Q₂Q₁'Q₀ (Table 36.2a)

D₁ = Q₁'Q₀'X + Q₁'Q₀X' + Q₁Q₀'X' + Q₁Q₀X which simplifies to D₁ = Q₀ ⊕ Q₁ ⊕ X (Table 36.2b)

D₀ = Q₀' (Table 36.2c) — The least significant bit toggles on every clock pulse.

🔑 Definition — D flip-flop input table: A table listing the required D input values for each flip-flop to transition from present state to next state. 📐 Formula: D₁ = Q₀ ⊕ Q₁ ⊕ X → The D₁ input equals the XOR of the three variables Q₀, Q₁, and X. 📌 Example: When present state Q₂Q₁Q₀=010 and X=0, the next state is 011. D₂=0, D₁=1, D₀=1 as shown in Table 36.1a, row 3.

The circuit diagram (Figure 36.1) shows three D flip-flops with their D inputs connected according to these Boolean expressions.

ABEL Implementation — Equation Definition

The ABEL input file defines pin assignments: pins 1,2,3 are CLOCK, CLEAR, X; pins 21,22,23 are Q₀, Q₁, Q₂. The outputs are declared as ISTYPE 'reg,buffer' since they are sequential outputs from flip-flops.

Table 36.3a shows the pin definitions. The state variables Q₀, Q₁, Q₂ define the different counter states.

The ABEL equations (Table 36.3b) define next state outputs:

Q0 := !Q0;
Q1 := Q0 $ Q1 $ X;
Q2 := !Q2 & !Q1 & !Q0 & X # !Q2 & Q1 & Q0 & !X # Q2 & !Q0 & !X 
      # Q2 & Q1 & X # Q2 & !Q1 & Q0;

The statements [Q0, Q1, Q2].CLK = clock and [Q0, Q1, Q2].AR = !clear declare state changes occur on clock transitions, and the Asynchronous Reset (AR) clears all flip-flops when clear is active low.

The Test Vectors (Table 36.3c) verify the counter operation. The first vector with Clear=0 resets outputs to 000 regardless of X input. When Clear=1 and X=0, the counter increments: 000→001→010→011→100→101→110→111→000. When X=1, it decrements: 111→110→101→100→011→010→001→000.

💡 Why this matters: Test vectors are essential for verifying sequential circuit functionality before hardware implementation.

Using a Truth-Table to specify Sequential Circuit

The ABEL Input file can use a truth table instead of equations to specify the Boolean expressions. The Equation definition reduces to two statements defining clock transition and asynchronous reset (Table 36.4a).

The Truth Table (Table 36.4b) has inputs [Clear, X, Q₂, Q₁, Q₀] and outputs [Q₂, Q₁, Q₀]. The first statement shows that when Clear=0, the output resets to 000 regardless of other inputs. The next 16 statements define the 8 input combinations for up counting (X=0) and 8 for down counting (X=1).

🔑 Definition — Truth table specification: An alternative to Boolean equations where the complete circuit behavior is defined by listing all input combinations and their corresponding next state outputs.

📌 Example: When Clear=1, X=0, Q₂Q₁Q₀=011, the next state is 100 (incrementing from 3 to 4).

Using a State Diagram to specify Sequential Circuit

The ABEL Input file can also use a State Diagram to specify the sequential circuit. First, states must be defined. Table 36.5a defines eight states A through H corresponding to Q₂Q₁Q₀ values 000 through 111.

The QSTATE variable groups the three state bits as [Q2, Q1, Q0].

Using IF-THEN-ELSE statements (Table 36.5b): For State A, "if X then H else B" means if X=1 (count down) go to state H (111), else go to state B (001, count up). Similar statements define transitions for all eight states.

Using GOTO statements (Table 36.5c): For a simple up counter, unconditional transitions are specified: State A goes to B, B to C, C to D, D to E, E to F, F to G, G to H, H to A.

🔑 Definition — State Diagram: A graphical representation showing states as nodes and transitions as directed edges with input conditions. 📐 Formula: State A: if X then H else B → If X=1, next state is H; if X=0, next state is B. 📌 Example: In the up counter GOTO specification, from State D (011, value 3), the next state is E (100, value 4).

Design Example: Elevator Control System

An elevator system in a building moves between floors. Users press request buttons, floor selection buttons, and an open door button. The elevator has a 7-segment display showing the current floor and direction.

Input and Output Signals:

• Inputs: REQ1, REQ2 (call elevator), FLOOR1, FLOOR2 (floor selection), OPEN (door open button), CLOCK, ARRIVE (floor sensor)
• Outputs: DOOR (0=open, 1=closed), DIR (0=up, 1=down), MOTION (0=waiting, 1=moving)

💡 Why this matters: This illustrates how sequential state machines control real-world systems with multiple inputs and outputs.

Elevator State Diagram

The state diagram (Figure 36.2) has six states requiring three state variables:

Wait 1 State (W1) — State 000: Elevator waiting on floor 1, door open. Outputs: DOOR=0, MOTION=0, DIR=0. Transitions to C1 if no request, or to UP if REQ2 or FLOOR2 is pressed.

Close 1 State (C1) — State 100: Elevator on floor 1, doors closed. Outputs: DOOR=1, MOTION=0, DIR=0. Returns to W1 if OPEN or REQ1 is pressed.

Up State (U) — State 110: Elevator moving up. Outputs: DOOR=1, MOTION=1, DIR=0. Transitions to W2 when ARRIVE signal received.

Wait 2 State (W2) — State 001: Elevator waiting on floor 2, door open. Outputs: DOOR=0, MOTION=0, DIR=1. Transitions to C2 if no request, or to D if REQ1 or FLOOR1 pressed.

Close 2 State (C2) — State 101: Elevator on floor 2, doors closed. Outputs: DOOR=1, MOTION=0, DIR=1. Returns to W2 if OPEN or REQ2 pressed.

Down State (D) — State 111: Elevator moving down. Outputs: DOOR=1, MOTION=1, DIR=1. Transitions to W1 when ARRIVE signal received.

State Table

Table 36.6a shows next states for REQ1, FLOOR1, and OPEN inputs. Table 36.6b shows next states for REQ2, FLOOR2, and OPEN inputs.

For example, from W1 state: if REQ2=0, next state is C1; if REQ2=1, next state is UP. From C1 state: if REQ2=0, stay in C1; if REQ2=1, go to UP.

🔑 Definition — State Table: A tabular representation showing present states, input conditions, and corresponding next states. 📌 Example: From W1 (000), if FLOOR2=1, the next state is UP (110) — elevator starts moving to floor 2.

Input Latches

Request buttons (REQ1, REQ2), floor buttons (F1, F2), and OPEN button can be pressed at any time. If a button is pressed and released between clock transitions, the sequential circuit might miss the input. Therefore, all input buttons must be connected through latches not controlled by a clock signal (Figure 36.3).

A total of 5 latches are required to store inputs from REQ1, REQ2, F1, F2, and OPEN. These latches capture and hold the button states until the state machine processes them.

🔑 Definition — Input Latch: An asynchronous storage element that captures and holds an input signal until it is read by the sequential circuit. 📌 Example: A person presses REQ1 momentarily between clock cycles; the latch stores this request so the state machine detects it at the next clock edge.

⭐ Key Takeaways

The 3-bit Up/Down counter demonstrates three equivalent ABEL specification methods — equations, truth tables, and state diagrams — each useful for different design scenarios. The D flip-flop implementation simplifies to D₁=Q₀⊕Q₁⊕X and D₀=Q₀', with D₂ requiring a more complex expression. The elevator control system exemplifies a practical Mealy/Moore state machine with six states, five button inputs, an ARRIVE sensor, and three output signals controlling doors, direction, and motion. Input latches are essential to capture asynchronous button presses that may occur between clock cycles, ensuring no requests are missed.

🧠 Quick Revision Questions

1. What are the three methods of specifying a sequential circuit in ABEL, and what are the advantages of each?
2. Why must asynchronous input buttons like REQ1 and OPEN be connected through latches in the elevator control system?
3. What is the simplified Boolean expression for D₁ in the 3-bit Up/Down counter, and how is it derived from the Karnaugh map?
4. How does the state diagram for the elevator switch from Wait 1 State to Up State, and what input conditions trigger this transition?
5. In the 3-bit Up/Down counter test vectors, what happens when Clear=0 and why is this behavior important for circuit initialization?

📘 Lecture 37 — Reduced Number of Input Latches

📖 Overview: This lecture focuses on reducing the number of input latches in the elevator control system from five to two (SR1 and SR2), simplifying the Boolean expressions and circuit design. It also introduces a new design example of a Traffic Signal Control System, covering its inputs, outputs, and state machine implementation using ABEL.

🗂️ Topics Covered

This lecture covers the simplification of the elevator control system by using two SR latches (SR1 and SR2) to store external inputs like REQ1, FLOOR1, OPEN, REQ2, FLOOR2, and OPEN. It presents the simplified next state tables for both latches and the overall next state table based on SR1, SR2, and ARRIVAL inputs. The lecture then details the complete ABEL input file for the elevator state machine, including pin declarations, state definitions, and state diagrams. Finally, it introduces a new design example: a Traffic Signal Control System, outlining its sensors, timing inputs, outputs, and state machine design.

📝 Lecture Summary

Reduced Number of Input Latches

The number of latches used to store external inputs in the elevator control system can be reduced to two. The REQ1, FLOOR1, and OPEN button outputs (pressed when the elevator is on the first floor) are stored on one latch, and the REQ2, FLOOR2, and OPEN button outputs (pressed when the elevator is on the second floor) are stored on a second latch. This reduces the complexity of the Boolean expressions for the next state excitation inputs.

The Boolean expressions that set the latch SR1 is: REQ1 + FLOOR1.DIR + OPEN.DIR. The DIR variable indicates the current floor: if DIR=0, the elevator is on the first floor; if DIR=1, it is on the second floor. The circuit diagram for the SR1 latch shows the set and reset inputs derived from these signals.

🔑 Definition — DIR variable: indicates the current floor. DIR=0 means the elevator is on the first floor, DIR=1 means it is on the second floor.

The simplified next state table for inputs REQ1, FLOOR1, and OPEN in terms of the SR1 latch is shown in Table 37.1. For example, when the present state is C1(100) and SR1=0, the next state is C1; when SR1=1, the next state is W1.

The state of inputs REQ2, FLOOR2, and OPEN is similarly represented by the second latch SR2. The circuit diagram and Boolean expression follow the same logic, as shown in Figure 37.2 and Table 37.2.

In the modified block diagram (Figure 37.3), the Next State Combinational Circuit block is replaced by latches SR1 and SR2, which handle the external inputs. The external input ARRIVE is connected directly to the Next State Combinational circuit along with the Present State inputs to determine the excitation inputs for the memory element.

The overall Next State Table (Table 37.3) for the Elevator State Machine is based on the SR1, SR2, and ARRIVAL inputs. It determines the next state for each combination of present state and these input conditions.

The ABEL Input file for Elevator State Machine

The ABEL input file for the Elevator State Machine defines the pin declarations, state definitions, state diagram, and equations for the latches.

The SR1, SR1_, SR2, and SR2_ variables are the Q and Q̄ (NOT Q) outputs for latches SR1 and SR2. These outputs are generated by combinational circuits and are defined as ISTYPE 'com.buffer'. These outputs are fed back to the AND gate array. The outputs from the three D flip-flops (DOOR, MOTION, and DIR) are declared as ISTYPE 'reg.buffer' as they are sequential circuit outputs.

The pin declarations (Table 36.4a) map the CLK, !OLE, REQ1, REQ2, FLOOR1, FLOOR2, OPEN, ARRIVE inputs to specific pins and the SR1, SR1_, SR2, SR2_, DOOR, MOTION, and DIR signals to output pins.

The states are defined using statements like WAIT1 = ^B000;, CLOSE1 = ^B100;, etc. (Table 37.4b).

The state diagram (Table 37.4c) defines the operation of the sequential state machine using State_diagram CONSTATE and statements for each state (e.g., State WAIT1: if (SR2) then UP else CLOSE1;).

The equations for the latches SR1 and SR2 are defined in the Equation Definition part (Table 37.4d). For example:

• SR1 = REQ1 # !DIR.FB & OPEN # DIR.FB & FLOOR1 # !SR1_;
• SR1_ = (!DOOR.FB & !MOTION.FB & !DIR.FB) # !SR1;

The 'FB' indicates that the DOOR, MOTION, and DIR output signals are fed back to the AND gate array.

Design Example: Traffic Signal Control System

This lecture introduces a new design example: a Traffic Signal Control System at a road intersection. On each road section, two sensors determine the presence and arrival of vehicles:

• Sensor 1: activated if a car is waiting.
• Sensor 2: activated when an arriving vehicle passes over it.

Sensors on the North-South section are connected together, determining the presence of vehicles on that road. Similarly, sensors on East-West are connected together.

During the day, the traffic light is cycled every 5 minutes: Green for 5 minutes, then Red for 5 minutes for each section. During the night, it stops a car for a maximum of 1 minute, unless a car approaches on the cross road, in which case the signal turns red for the approaching car and allows the waiting car to proceed.

Traffic Signal Controller Inputs and Outputs:

• NSSR: activated when a car is over any of the four sensors on the North-South section.
• EWSR: activated when a car is over any of the four sensors on the East-West section.
• LTIME: activated if 5 minutes have elapsed.
• STIME: activated if 1 minute has elapsed.
• NSGrn, NSYel, NSRed: Green, Yellow, and Red signals for North-South traffic.
• EWGrn, EWYel, EWRed: Green, Yellow, and Red signals for East-West traffic.
• TMRST: Resets the timer after a time interval is reached.

The transition from the NSG (North-South Green) state to the NSY (North-South Yellow) state is determined by a flowchart (Figure 37.5) based on inputs like LTIME, STIME, EWSR, and NSSR.

The state machine can be implemented using a GAL16V8 device. The pin declarations (Table 37.5a) define pins for CLOCK, NSSR, EWSR, LTIME, STIME, state variable outputs Q0, Q1, Q2 (defined as ISTYPE 'reg.invert'), and TMRST (defined as ISTYPE 'com.invert').

The states (Table 37.5b) are defined using three state variables (e.g., NSG = [0, 0, 0]; NSY = [0, 0, 1];).

The ABEL State Diagram statements (Table 37.5c) define each state and transitions. For example:

State NSG: if (!STIME) then NSG
           else if (LTIME) then NSY
           else if (EWSR & !NSSR) then NSG
           else if (EWSR & NSSR) then NSY
           else if (!NSSR) then NSG
           else NSY;

💡 Why this matters: This design example demonstrates a practical application of state machines in real-world control systems, showing how to handle multiple conditions and timing constraints.

⭐ Key Takeaways

The key takeaway is that reducing the number of input latches in a state machine simplifies both the hardware design and the Boolean expressions, as demonstrated by the elevator controller. The ABEL input file is crucial for implementing state machines in PLDs, using pin declarations, state definitions, and state diagrams. The Traffic Signal Control System example illustrates a complex real-world application involving multiple sensors, timers, and state transitions based on various conditions (day/night mode, car presence on different roads). Understanding how to define states, derive transition conditions from flowcharts, and implement them in ABEL is essential for designing control systems.

🧠 Quick Revision Questions

1. What is the benefit of reducing the number of latches in the elevator control system, and which two latches are used instead of five?
2. What is the Boolean expression for setting the SR1 latch, and what does the DIR variable represent in that expression?
3. In the ABEL file for the elevator controller, what are the ISTYPE declarations for SR1/SR2 and DOOR/MOTION/DIR, and why are they different?
4. In the Traffic Signal Control System, what is the function of the LTIME and STIME inputs, and during which operation mode (day or night) does each apply?
5. Describe the state transition conditions from the NSG state to the NSY state in the Traffic Light Controller, based on the given flowchart.

📘 Lecture 38 — EQUATION DEFINITION

📖 Overview: This lecture focuses on the equation definition and circuit implementation of a Traffic Light Controller using GAL16V8 devices. It then shifts to the analysis of Clocked Synchronous State Machines, covering how to derive the next-state and output functions from a given circuit to construct state tables and state diagrams.

🗂️ Topics Covered

The lecture begins by defining the equations for the Traffic Controller's state machine and timer, along with the circuit diagram showing connections to two GAL16V8 chips for state control and lamp switching. The ABEL input file with pin declarations and equations for turning on/off the six traffic lamps (NSRED, NSYEL, NSGRN, EWRED, EWYEL, EWGRN) is detailed, including the Manual mode for flashing yellow lamps. The second half covers the analysis procedure for Clocked Synchronous State Machines, focusing on deriving characteristic equations for flip-flops and providing two complete analysis examples: one using D flip-flops (yielding a 2-bit counter) and another using J-K flip-flops, both demonstrating the construction of transition tables, state tables, and state diagrams for Mealy and Moore machines.

📝 Lecture Summary

Equation Definition

The Traffic Controller uses equation definitions to define the TRSTATE variable, which is dependent upon the clock transition. The Timer is reset when the state is either NSY2 or EWY2.

🔑 Definition — TRSTATE.CLK: The clock input for the traffic controller state register. 🔑 Definition — TMRST: The timer reset signal. It is set to logic high when the current state is NSY2 or EWY2.

📐 Formula: TMRST := (TRSTATE == NSY2) # (TRSTATE == EWY2); → The timer is reset (TMRST = 1) when the traffic controller state equals NSY2 OR EWY2.

📌 Example: Table 38.1 shows this equation definition. When the state machine is in either the NSY2 or EWY2 state, the combinational logic asserts the TMRST signal, resetting the external timer to begin its countdown for the next traffic light phase.

The circuit diagram of the Timer connected to the GAL16V8 based Traffic Light Controller

The circuit diagram (Figure 38.1) shows a Traffic Light Controller built around two GAL16V8 programmable logic devices. The first GAL16V8 is connected to external inputs NSSR, EWSR, and the CLK signal. It also receives two timer signals: LTIME and STIME, which determine the Green cycle time during day and night respectively. The output of the first controller is TMRST, which resets the Timer when the Controller is in state NSY2 or EWY2. The state outputs Q0‾, Q1‾, and Q2‾ (inverted state outputs) are connected to the input of the second GAL16V8. This second chip is programmed as a combinational circuit to turn on/off the traffic signal lights: NSRED, NSYEL, NSGRN, EWRED, EWYEL, and EWGRN. The chip is also connected to MANUAL and FLASHCLK inputs. When MANUAL is activated, it puts the traffic signal in Manual Mode, where the Yellow signal on both road sections repeatedly flashes, with the flash rate determined by the FLASHCLK signal.

Switching of Traffic Lights

The main definitions and declarations of the ABEL input file for turning on/off the traffic lights are given (Table 38.2). The Pin Declarations (Table 38.2a) assign inputs and outputs to specific pins on the GAL16V8:

• FLASHCLK, MANUAL → pins 1, 2
• !Q0, !Q1, !Q2 (inverted state variables) → pins 4, 5, 6
• NSRED, NSYEL, NSGRN → pins 19, 18, 17
• EWRED, EWYEL, EWGRN → pins 14, 13, 12

The Red, Yellow, and Green signals are turned on/off at different states, as shown in Table 38.2b. For example, in state NSG, the North-South Green is on, and the East-West Red is on. In state NSY, the North-South Yellow is on. In state EWG, the East-West Green is on.

📐 Formula (Equations for turning on/off traffic lamps - Table 38.2c):

• NSRED = !MANUAL & (TRSTATE !=NSG) & (TRSTATE != NSY) & (TRSTATE != NSY2);
• NSYEL = !MANUAL & ((TRSTATE == NSY) # (TRSTATE == NSY2)) # MANUAL & FLASHCLK;
• NSGRN = !MANUAL & (TRSTATE == NSG);
• EWRED = !MANUAL & (TRSTATE !=EWG) & (TRSTATE != EWY) & (TRSTATE != EWY2);
• EWYEL = !MANUAL & ((TRSTATE == EWY) # (TRSTATE == EWY2)) # MANUAL & FLASHCLK;
• EWGRN = !MANUAL & (TRSTATE == EWG);

The equations show that when MANUAL is inactive (!MANUAL = 1), the lights are controlled by the current state (TRSTATE). When MANUAL is active, NSYEL and EWYEL flash based on the FLASHCLK signal. 💡 Why this matters: The !MANUAL term ensures the automatic controller is disabled in manual mode, while the # MANUAL & FLASHCLK term forces the yellow lamps to toggle with the flash clock.

Analysis of Clocked Synchronous State Machines

Analysis of a Clocked Synchronous State Machine is the opposite process of Design and Implementation. The goal is to take an implemented circuit and describe its behavior using a state table or state diagram. The analysis procedure has three basic steps:

1. Determine the next-state and output functions F and G:
   • Next State = F(Current State, Input)
   • Output = G(Current State, Input)
2. Use the functions F and G to construct a state/output table.
3. Draw a State diagram that represents the information in graphical form.

The functional behavior of a flip-flop is described by a characteristic equation. This equation is a function of its current state and inputs and describes the functional response, not the timing. The characteristic equations can be derived from excitation tables using Karnaugh maps.

🔑 Definition — Characteristic Equation: A boolean equation that defines the next state (Q(t+1)) of a flip-flop as a function of its current state (Qt) and its inputs (e.g., S, R, D, J, K).

📐 Formula (S-R Latch Characteristic Equation): Q(t+1) = S + R‾‾ * Qt → The next state is '1' if the Set input is 1, OR if we are not Resetting (R=0) and the current state is 1.

📌 Example (Deriving S-R Latch Characteristic Equation): The S-R Latch transition table (Table 38.3) shows that for an output transition from 0 to 1, the inputs must be S=1, R=0 or S=1, R=x. The information is mapped to a 3-variable K-map (Figure 38.2), which simplifies to the characteristic equation Q(t+1) = S + R‾‾ * Qt.

📐 Formula (Characteristic Equations for various flip-flops - Table 38.4):

State Machine Analysis Example 1

A State Machine with two positive-edge triggered D flip-flops is shown in Figure 38.3. The two flip-flops transfer their D input values to their outputs. The excitation inputs to the two D flip-flops are determined by the combinational circuit.

📐 Formula (Excitation Equations for D0 and D1 - Table 38.5):

• D0 = Q0‾‾ * EN + Q0 * EN‾
• D1 = Q1‾‾ * EN + Q0‾ * Q1 * EN + Q0 * Q1‾ * EN

Using the D flip-flop characteristic equation (Q(t+1) = D), the Transition Equations are: 📐 Formula (Transition Equations for Q0 and Q1 - Table 38.6):

• Q0(t+1) = Q0‾ * EN + Q0 * EN‾
• Q1(t+1) = Q1‾ * EN + Q0‾ * Q1 * EN + Q0 * Q1‾ * EN

From these transition equations, a Transition Table is prepared (Table 38.7). The output is defined by: MAX = Q0 * Q1 * EN. Because the output depends on the input (ENABLE), this is a Mealy Machine. The State Table (Table 38.8) assigns state names (A, B, C, D) to the Q1Q0 values (00, 01, 10, 11). The resulting machine is a 2-bit Counter that increments when ENABLE=1 and holds when ENABLE=0. The MAX output is 1 only when the state is D (11) and the input is 1.

📌 Example: If the current state is D (Q1Q0=11) and ENABLE=1, the next state is A (Q1Q0=00) and the output MAX=1. If the output were only dependent on the current state and not the input, it would be a Moore Machine (Table 38.9). The corresponding state diagrams are shown in Figures 38.4 (Mealy) and 38.5 (Moore). In the Mealy diagram, the output is written on the transition arrow (input/output), while in the Moore diagram, the output is written inside the state circle.

State Machine Analysis Example 2

A State Machine with two edge-triggered J-K flip-flops is shown in Figure 38.6. The two sets of excitation equations are:

📐 Formula (Excitation Equations for J0, K0, J1, K1 - Table 38.10):

• J0 = X * Y
• K0 = X‾ * Y‾ + Q1 * Y
• J1 = X * Q0‾ + Y‾
• K1 = Q0‾ * Y + X * Y * Q0

Using the J-K flip-flop characteristic equation (Q(t+1) = J * Q‾ + K‾ * Q), the Transition Equations are derived through boolean algebra.

📐 Formula (Simplified Transition Equations - Table 38.11):

• Q0(t+1) = X * Y * Q0‾ + X‾ * Q1 * Q0 + X‾ * Y * Q0 + Y * Q1 * Q0
• Q1(t+1) = X * Q0‾ * Q1 + Y‾ * Q1 + X * Q0 * Q1 + Y‾ * Q0 * Q1 + X‾ * Y * Q1 + Y * Q0 * Q1

A Transition Table is then prepared (Table 38.12) showing the next state for all four combinations of present state (Q1Q0) and inputs (X,Y). The output equation is: Z = X * Q0 * Q1‾ + Y‾ * Q0‾ * Q1. Since the output Z depends on the inputs (X, Y), this is a Mealy Machine. The State Table (Table 38.13) assigns state names to the Q1Q0 values. The corresponding State Diagram is shown in Figure 38.7.

📌 Example: If the present state is A (Q1Q0=00) and the inputs are XY=01, the next state is C (Q1Q0=10) and the output Z=1.

⭐ Key Takeaways

• The Traffic Light Controller uses two GAL16V8 chips: one for the state machine and timer control (with equations defining TRSTATE and TMRST), and another for decoding states into specific lamp outputs (NSRED, NSYEL, etc.), including a Manual flash mode.
• The Analysis of a Clocked Synchronous State Machine is the reverse of design; it involves deriving next-state and output equations from a circuit, constructing a transition table, and then creating a state table and state diagram.
• Each flip-flop type has a distinct characteristic equation (e.g., Q(t+1) = D for D-FF, Q(t+1)=JQ' + K'Q for JK-FF) which describes its next-state behavior and is essential for analysis.
• The key difference between a Mealy and Moore machine is that a Mealy machine's output depends on both the current state and the inputs, while a Moore machine's output depends only on the current state. This is reflected in the state diagram and state table.
• A multi-variable transition table lists all possible next states for every combination of present state and inputs. Assigning state names (A, B, C, D) to the binary state vectors creates the more abstract state table.

🧠 Quick Revision Questions

1. What is the purpose of the TMRST signal in the Traffic Light Controller, and when is it activated?
2. What are the three main steps in the procedure for analyzing a Clocked Synchronous State Machine?
3. Write the characteristic equation for a J-K flip-flop. What does each term represent?
4. In State Machine Analysis Example 1, what specific circuit function (e.g., counter, shift register) does the D flip-flop based machine implement?
5. What is the fundamental difference in the state/output table between a Mealy machine and a Moore machine?

📘 Lecture 39 — MEMORY

📖 Overview: This lecture introduces the fundamental concepts of computer memory systems, covering memory organization, capacity, and the basic operations of reading and writing data. It explains the different types of memory, including RAM and ROM, and delves into the internal structure and operation of static RAM cells and arrays, which is essential for understanding how digital systems store and retrieve information.

🗂️ Topics Covered

The lecture begins with an introduction to memory elements in sequential circuits and computer systems, followed by memory organization in terms of cells, nibbles, bytes, and words. It then covers memory capacity and density, the signals and basic operations on memory including read and write operations, and concludes with a detailed explanation of memory types—specifically Random Access Memory (RAM) and Read-Only Memory (ROM)—with a focus on Static RAM and its internal cell structure and array organization.

📝 Lecture Summary

Basic Memory Concepts

Sequential circuits require memory elements, which are relatively small for storing few binary bits. Large memories in computer systems store application programs as program instructions. Memories store data in units of bits (smallest unit), nibbles (4-bit unit), and bytes (8-bit unit, composed of two nibbles). A word is a complete unit of information consisting of one or more bytes.

Each storage element is called a cell, capable of storing a logic 0 or logic 1. Memories are arranged in an array where each cell can be identified by a row and column number. For example, in a 64-cell memory array (8 x 8), the first row stores eight bits of binary information (e.g., 11001010). Individual cells at row 5, column 3 store a binary 1, and at row 6, column 7 store a binary 0.

Memory Organization

A memory array can be organized based on the unit of data. A 64-cell array (8 x 8) is considered an 8-byte memory with eight locations, each storing a single byte. The same array organized as 4 x 16 stores 16 nibbles, and as 1 x 64 stores 64 single-bit values. A memory is identified by the number of units it can store times the unit size: an 8 x 8 memory is an 8-byte memory, a 16 x 4 memory is a 16-nibble memory, and a 64 x 1 memory is a 64-bit memory. Practical memory chips are organized as 16K x 8 (storing 16K bytes or 16 x 1024 = 16384 bytes) or 32K x 4 (storing 32K nibbles or 32 x 1024 = 32768 nibbles).

🔑 Definition — Nibble: A 4-bit unit of data. 🔑 Definition — Byte: An 8-bit unit of data, composed of two nibbles.

Memory Capacity and Density

Memory capacity is the maximum amount of information a memory array can store in bits. For example, a 16K x 8 memory stores 16K bytes (131072 bits), and a 32K x 4 memory stores 32K nibbles (131072 bits). The total number of cells in both cases is 131072. Memory density specifies the number of bits stored per unit area—the more bits stored per unit area, the denser the memory. Capacity and density are determined by the total number of cells implemented per unit area.

Memory Signals and Basic Operations on Memory

Two basic operations are performed on memories: reading information from the memory and writing data to the memory. Memories provide several signals to support these operations, as shown in a block diagram of a read-write memory.

🔑 Definition — Read/Write Signal: A signal that configures the memory for read or write operation. When set high, data is read from memory; when set low, data is written into memory. Some chips have separate Read and Write signals.

🔑 Definition — Address Signals: Signals that specify the memory location from which information is accessed. A set of parallel address lines (the address bus) carries the address. The number of address bits depends on memory size—for example, a memory with four locations requires a 2-bit address bus.

📐 Formula: ( 2^n ) → The number of uniquely addressable locations, where ( n ) is the number of address bits. Thus, ( 2^4 = 16 ) means 4 bits identify 16 locations.

🔑 Definition — Data Signals: Lines used to retrieve information during read operations and to provide data for storage during write operations. The number of data lines equals the number of data bits stored at each addressable location. For example, a byte-organized memory requires an 8-bit data bus, while a nibble-organized memory requires a 4-bit data bus.

🔑 Definition — Memory Select or Enable Signal: A chip enable or chip select signal that must be activated before a memory chip can be accessed in a computer system with multiple memory chips.

Memory Read Operation

The memory read operation proceeds as follows:

1. The memory chip is selected by activating the Memory Select signal.
2. The Read signal is asserted to configure the memory for reading.
3. An address (e.g., 100) is applied on the Address Lines.
4. The internal address decoder decodes the address and selects one unique row.
5. The data at that location (e.g., 00110001) is read and placed on the data bus.
6. The microprocessor latches this data into its data buffer.

📌 Example: A microprocessor places address 100 on the address bus. The internal address decoder activates row select line 4. Data at location 4 (00110001) is placed on the data bus and stored in the microprocessor's data buffer.

Memory Write Operation

The memory write operation proceeds as follows:

1. The memory chip is selected by activating the Memory Select signal.
2. The Write signal is asserted to configure the memory for writing.
3. An address (e.g., 011) is placed on the Address Lines by the microprocessor.
4. The internal address decoder decodes the address and selects one unique row (location 3).
5. The data to be written (e.g., 10110010) is placed on the data bus by the microprocessor and stored at the selected location.

📌 Example: A microprocessor places address 011 on the address bus, activating row select line 3. The microprocessor also places data 10110010 on the data bus, which is stored at location 3.

💡 Why this matters: The address decoder is critical because it ensures that only the correct memory location is accessed during read and write operations, preventing data corruption.

Memory Types

Two major categories are Random Access Memory (RAM) and Read-Only Memory (ROM).

• RAM allows read or write operations at any address, with all locations accessible in equal time. RAM is volatile—data is lost when power is turned off.
• ROM retains data permanently even when power is off—it is non-volatile. ROM is programmed by the manufacturer and contains critical information for starting (booting) the computer. Users cannot write information to ROM chips.

Random Access Memory (RAM)

RAM is divided into two types:

• Static RAM (SRAM): Uses flip-flops as storage elements. Each cell retains information as long as power is supplied. SRAM is faster than DRAM.
• Dynamic RAM (DRAM): Uses capacitors to store binary information. A charged capacitor stores a binary 1, and an uncharged capacitor stores a binary 0. Capacitors lose charge over time, so a Refresh cycle is required periodically. DRAM has higher density and lower cost than SRAM but is slower.

Static RAM

Each cell of a Static RAM is implemented using a flip-flop made of several MOSFET transistors. As long as external power is applied, the static memory cell retains data. In the flip-flop based cell:

• When the SEL signal is activated, the output buffer is enabled, allowing data to be read.
• When both SEL and W(rite) signals are activated, the latch is in transparent mode, and data from the Data In line flows to the output.
• Data In and Data Out lines can be connected to form a bi-directional line, as read and write operations occur at different times.

An 8 x 4 Static RAM array combines flip-flop cells with additional logic:

• A 3 x 8 decoder decodes a 3-bit address to select one of eight locations, each comprising a group of 4 cells.
• For address 000, the first output line activates the SEL input of the four latches in the first row. Address 111 activates the eighth row.
• The memory has four Data In lines (Data In 3 = MSB, Data In 0 = LSB) and four Data Out lines.
• Read and write operations are controlled by W (Write), CS (Chip Select), and OE (Output Enable) signals. The CS and OE signals enable tri-state buffers on the Data Out lines for reading. The W and CS signals are used to write data.

📌 Example: To write data 1001 at the 6th memory location, address bits A₂, A₁, A₀ are set to 110, selecting the 6th row. Data 1001 is placed on the four Data In lines. The CS and W signals activate the four latches in the sixth row to transparent mode, making the data available at the Q outputs. When CS and W are deactivated, the latches store the data value.

A 16K x 8 memory stores byte values in 16 × 1024 locations. Fourteen address lines are required to address these locations, and eight bi-directional data lines are used for read/write operations. The CS, WE, and OE signals are active low.

⭐ Key Takeaways

Memories store data in cells arranged in arrays, organized as bits, nibbles, or bytes, and are identified by their unit count and size. Two fundamental operations—read and write—rely on address, data, and control signals, with the address decoder selecting specific locations. RAM is volatile and allows both reading and writing, while ROM is non-volatile and read-only. Static RAM uses flip-flops for fast, reliable storage but has lower density than Dynamic RAM, which uses capacitors requiring periodic refresh. The internal structure of SRAM arrays, including decoders and tri-state buffers, is essential for understanding how data is accessed and stored in digital systems.

🧠 Quick Revision Questions

1. What is the difference between a nibble and a byte in terms of bit count, and how are they related?
2. A memory chip has 12 address lines. Use the formula ( 2^n ) to determine how many unique locations it can address.
3. Describe the sequence of steps required to perform a read operation on a memory chip.
4. Why is Dynamic RAM (DRAM) considered volatile, and what mechanism is required to prevent data loss?
5. In an 8 x 4 Static RAM, what is the role of the 3 x 8 decoder, and how does it interact with the Chip Select (CS) and Write (W) signals during a write operation?

📘 Lecture 40 — Decoding Large Memories

📖 Overview: This lecture covers the architecture and operation of large memory systems, focusing on row and column decoders for faster access. It explains memory read/write cycles, synchronous burst SRAM, dynamic RAM (DRAM) cells, and address multiplexing techniques used to reduce pin count in modern memory chips.

🗂️ Topics Covered

The lecture introduces memory array decoding using row and column decoders, input/output data buffer circuits, memory read and write timing cycles, synchronous burst SRAM architecture with its burst logic circuitry, DRAM cell operation including writing, reading, and refreshing, and address multiplexing using RAS and CAS signals in DRAM chips.

📝 Lecture Summary

Decoding Large Memories

Large memories like 16 KB use row and column decoders to split the input address into a row address and a column address, activating respective select lines. This two-dimensional arrangement speeds up decoding compared to linear address methods. As memories get larger, splitting addresses into row and column components requires smaller decoders with fewer gates, resulting in faster decoding times and faster memory access.

Input/Output Data Circuit

The Input/Output Buffer manages data flow. When the W (write) signal is active and the chip is selected (CS active), the top AND gate enables data writing to latches. When W is inactive but CS and OE (output enable) are active, the bottom AND gate enables tri-state buffers, allowing data from latches to appear on the bi-directional Data In/Out lines.

Memory Read Cycle

The Read Cycle begins by applying stable address signals for duration tRC (read cycle time). After activating CS and OE, valid data appears after delay tGQ (output enable access time). tAQ (address access time) is measured from valid address appearance to valid data on data lines. tEQ (chip enable access time) is the time for valid data after CS goes low.

Memory Write Cycle

The Write Cycle begins by applying stable addresses for duration tWC (write cycle time). The WE (write enable) signal activates after ts(A) (address setup time). The write pulse width is the duration WE stays active. Data must be applied after WE activates and remain valid for tWD minimum. Data must remain valid for th(D) (hold time) after WE deactivates.

Synchronous Burst SRAM

RAM chips are divided into Asynchronous SRAM (ASRAM) and Synchronous Burst RAM (SB SRAM). Asynchronous SRAM operation doesn't depend on clock signals. Synchronous SRAM uses a clock to synchronize read/write operations for faster performance. All inputs (address, WE, CS) are latched on the positive clock edge simultaneously. Two variations exist: Flow-through SRAM (no data output register, data available asynchronously) and Pipelined SRAM (has data output register that latches read data).

🔑 Definition — Burst feature: Allows synchronous SRAM to read or write up to four locations using a single address. The lower two address bits connect to Burst logic circuitry which internally increments addresses at each clock transition, producing four addresses (00, 01, 10, 11).

📌 Example: If external base address 37A0H is stored in the Address Register, the Burst Logic circuitry produces addresses 37A0, 37A1, 37A2, and 37A3.

Dynamic RAM (DRAM)

Static RAM uses 4-6 transistors per latch to store one bit. Dynamic RAM (DRAM) uses a single transistor and capacitor to store a binary value, occupying less space and allowing higher density. The capacitor stores charge representing logic 1 or 0. The drawback is capacitor discharge over time; periodic refreshing is required or data is lost, complicating DRAM operation.

🔑 Definition — DRAM cell write: The selected row activates the MOSFET, connecting the column line to the capacitor. R/W signal set low enables the Input Buffer. The logic value at DIN charges or discharges the capacitor via path A→B→D.

🔑 Definition — DRAM cell read: The selected row activates the MOSFET. R/W signal set high enables the Output Buffer. The stored charge on the capacitor is available at DOUT via path D→B→A.

🔑 Definition — Refresh cycle: The Refresh signal is set high enabling the Refresh Buffer. R/W is set high. Information from the capacitor passes through the Output Buffer/Sense Amplifier and is fed back to the capacitor through the Refresh Buffer via path C→B→D.

💡 Why this matters: Without periodic refresh (every few milliseconds), capacitors discharge and all stored data is lost, making refresh circuitry essential for DRAM operation.

Address Multiplexing

DRAM chips use address multiplexing to reduce address lines by half. The address is split into row address and column address. First, the row address is applied and latched by the Row Address Latch using the RAS (Row Address Strobe) signal. Then, the column address is applied on the same lines and latched by the Column Address Latch using the CAS (Column Address Strobe) signal.

🔑 Definition — Refresh cycle control: The Refresh Control and Timing circuit configures the Data Selector to select row addresses generated by the Refresh Counter. During refresh, all memory cells connected to the selected row are refreshed simultaneously.

📌 Example: A 1M bit DRAM arranged as 1024 rows × 1024 columns is refreshed by selecting all 1024 rows in sequence.

⭐ Key Takeaways

Students must understand that large memories use row and column decoders for faster access, with timing parameters like tRC, tAQ, tGQ, tEQ for reads and tWC, ts(A), tWD, th(D) for writes critical for proper operation. Synchronous Burst SRAM synchronizes all operations to a clock and can access four locations from one address using burst logic. DRAM stores bits using a single transistor-capacitor pair for higher density but requires periodic refresh cycles to prevent data loss. Address multiplexing using RAS and CAS strobes reduces the number of address pins on DRAM chips by half.

🧠 Quick Revision Questions

1. Why do large memories use row and column decoders instead of a single linear decoder?
2. What is the difference between tAQ (address access time) and tGQ (output enable access time) in a memory read cycle?
3. How does the burst feature in Synchronous SRAM generate four addresses from a single base address?
4. Explain the three operations (write, read, and refresh) in a DRAM cell showing the data paths involved.
5. How does address multiplexing reduce the number of address lines in DRAM, and what are the roles of RAS and CAS signals?

📘 Lecture 41 — READ AND WRITE CYCLES

📖 Overview: This lecture covers the read and write cycles of DRAM memory, including FAST Page Mode access, and explores various refresh methods. It then transitions to Read-Only Memory (ROM), detailing different types such as Mask ROM, PROM, EPROM, and EEPROM. Finally, it introduces FLASH memory, explaining its unique operations that combine the benefits of RAM and ROM.

🗂️ Topics Covered

The lecture begins with the detailed timing diagrams for DRAM Read and Write cycles. It then explains the FAST Page Mode for faster access to consecutive memory locations. The next section covers Burst Refresh and Distributed Refresh modes, followed by RAS only and CAS before RAS refresh techniques. The lecture then categorizes different types of DRAMs, including FPM, EDO, and Synchronous DRAM. The focus shifts to ROM, starting with a general architecture and then detailing specific types: Mask ROM, PROM, UV EPROM, and EEPROM. The internal structure of a 256 x 4 ROM is examined along with its application as a binary-to-gray code converter. The lecture concludes with a detailed discussion on FLASH memory, its storage cell structure, and its three primary operations: Programming, Read, and Erase.

📝 Lecture Summary

READ AND WRITE CYCLES

In a DRAM read cycle, the RAS and CAS signals are activated sequentially to latch the multiplexed row and column addresses. The R/W signal is activated to read data, which is then made available on the D_OUT data line. The write cycle is similar; the row and column addresses are applied with the strobe signals. The write signal is activated, allowing data placed on the D_IN data line to be stored in the selected memory cell.

🔑 Definition — Read Cycle: The process of activating RAS and CAS signals to latch the row and column addresses, and then activating the R/W signal to output data on the D_OUT line. 🔑 Definition — Write Cycle: The process of activating RAS and CAS to latch addresses, and then activating the R/W signal to store data from the D_IN line into the selected memory cell.

FAST Page Mode

In FAST Mode Page Access, all the columns in the same row are either read or written. A single row is considered a ‘Page’ of memory. The row address is latched by the RAS signal going low, and the RAS remains low throughout the page access. The CAS signal is toggled between high and low to select successive columns. Data is read or written to successive column locations. During the read cycle, when CAS goes high, the D_OUT line is disabled, so data must be latched by the external system before this occurs.

💡 Why this matters: FAST Page Mode significantly speeds up access when reading consecutive data from the same row, as the row address only needs to be set once.

📐 Formula: Access Time (FAST Page) < Access Time (Random Access) for consecutive addresses on the same row.

Burst Refresh and Distributed Refresh

DRAM chips are refreshed using either Burst Refresh Mode or Distributed Refresh Mode. In Burst Refresh, all rows in the DRAM chip are refreshed consecutively. For a DRAM with an 8 msec refresh cycle, a burst refresh of all rows occurs once every 8 msec. During this cycle, normal read/write operations are suspended. In Distributed Mode, the refresh cycle is interspersed between normal read/write cycles. For a 1024 x 1024 DRAM with an 8 msec refresh cycle, each of the 1024 rows must be refreshed every 7.8 microseconds.

🔑 Definition — Burst Refresh: A refresh mode where all rows are refreshed consecutively, preventing normal memory access during the cycle. 🔑 Definition — Distributed Refresh: A refresh mode where refresh cycles are interspersed between normal read/write cycles. 📐 Formula: Refresh Interval = Total Refresh Time / Number of Rows → For 8 msec / 1024 rows = 7.8 µs per row for distributed refresh.

RAS only Refresh and CAS before RAS Refresh

In RAS only refresh, the RAS signal goes low, latching the row address to be refreshed, while the CAS signal remains inactive high. An external counter provides the row addresses for the refresh operation. In CAS before RAS refresh, the CAS goes low before RAS goes low. This sequence activates an internal refresh counter that generates the row address to be refreshed, which is then switched by a data selector into the row decoder.

🔑 Definition — RAS only Refresh: A refresh method where an external counter provides row addresses, and the refresh is triggered by RAS. 🔑 Definition — CAS before RAS Refresh: A refresh method where an internal counter is automatically activated by the CAS signal going low before RAS, providing the row address.

Types of DRAMs

Several different types of DRAMs are available. Fast Page Mode DRAM (FPM) is faster for successive reads on the same row, but data on the D_OUT line must be latched before CAS is de-asserted. Extended Data Output (EDO) DRAM is similar to FPM, but the CAS signal doesn’t disable the D_OUT line. This allows the next column address to be accessed before the external system accepts the current data. Synchronous DRAM (SDRAM) operations are tied to a clock signal that also times the microprocessor, allowing for close synchronization.

🔑 Definition — Extended Data Output (EDO) DRAM: A DRAM type where the data output remains valid even after CAS goes high, allowing for faster access to the next column. 🔑 Definition — Synchronous DRAM (SDRAM): A DRAM type that uses a clock signal to synchronize its operations with the microprocessor. 💡 Why this matters: EDO DRAM improves read cycle speed by overlapping the fetching of the next address with the reading of current data, unlike FPM.

ROM Read-Only Memory

A ROM contains permanent data that cannot be changed. It does not allow a write operation. ROMs store data used repeatedly, such as tables, conversions, and programmed instructions for system initialization and operation. ROMs are non-volatile, meaning they retain data when power is turned off. Different types include Mask ROM (data stored during manufacturing), PROM (programmable once by user), EPROM (erasable and reprogrammable), UV EPROM (erased by UV light), and EEPROM (electrically erasable).

🔑 Definition — Read-Only Memory (ROM): A non-volatile memory type that stores permanent data and does not allow write operations.

Mask ROM

The storage cell in a Mask ROM is implemented using a MOS transistor. The Gate is connected to the row line and the output (Drain) is connected to the column line. When a row is selected, all transistors with their Gate connected to the row are turned on, connecting a high output to the column line. Transistors with their Gate connection removed are not turned on, and the corresponding column lines have a logic low output. During manufacturing, cells storing a logic 1 have their Gate connections intact, while cells storing a logic 0 have their Gate connections removed.

🔑 Definition — Mask ROM: A ROM where data is permanently stored by the presence or absence of a MOSFET gate connection during the manufacturing process.

ROM Architecture and Applications

A 16 x 8 ROM uses a 4-bit address decoded by a 4 x 16 decoder to select a row. MOSFETs connected to the selected row output a logic 1; those not connected output a logic 0. A terminating resistor on each column line ensures the output stays low when a MOSFET outputs a logic 0. A 256 x 4 ROM has an 8-bit address, split into a 5-bit row address (selecting one of 32 rows) and a 3-bit column address (selecting one of 8 column lines via four 8 x 1 Multiplexers). A common application is a look-up table, for example, converting a 4-bit binary value to a 4-bit Gray Code value, where the binary input is the address and the corresponding Gray Code is the stored data.

ROM Read Cycle & Access Time

The Access Time of a ROM is the time it takes for data to appear at the Data Output after an address is applied at the address input lines. It can also be measured from the activation of the chip enable (CS) signal to the appearance of valid data at the output lines.

🔑 Definition — Access Time (ROM): The time delay between applying a valid address (or activating chip enable) and the appearance of valid data at the output. 📐 Formula: Access Time = t_ACC (time from address valid to data valid) or t_CE (time from chip enable active to data valid).

PROM (Programmable ROMs)

A PROM can be programmed once by the user. It uses a fusible link to connect the output of the MOS transistor to the column line. When the fuse is intact, a logic high is seen on the column line when the cell is selected. When the fuse is blown, the column line outputs a logic low.

🔑 Definition — Programmable ROM (PROM): A ROM that can be programmed once by the user by selectively blowing fusible links within the memory array.

EPROM Erasable PROM

An EPROM is an Erasable PROM that uses an NMOSFET array with an isolated-gate structure. The isolated gate can store a charge indefinitely. The presence or absence of gate charge represents the data bit. UV EPROM is erased by exposing the chip to high-intensity UV light through a quartz window, neutralizing the charge after a few minutes. EEPROM (Electrically Erasable PROM) is erased electrically and can be programmed and erased in-circuit. For a 2 KB EPROM, 11 address lines (A0 to A10) and 8 data lines are needed. To read, the chip enable/program (CE/PGM) and output enable (OE) are set to active-low.

🔑 Definition — Erasable PROM (EPROM): A ROM that can be erased and reprogrammed, using a charge stored on an isolated gate to represent a data bit.

Programming EPROM

To program an EPROM, a high DC voltage is applied at the V_PP pin and the OE signal is set to logic high. The data to be programmed is applied to the 8 data lines, and the address is applied to the address lines. A high-level pulse is applied at the CE/PGM signal to program the data at the selected address. The entire EPROM is programmed by repeating this process for each address.

🔑 Definition — EPROM Programming: The process of applying a high voltage and specific control signals to store charge on the floating gate of selected memory cells.

EEPROM Electrically Erasable PROM

An Electrically Erasable PROM (EEPROM) is programmed and erased by applying electric pulses. It does not need to be exposed to UV light, allowing for rapid in-circuit programming and erasing.

🔑 Definition — Electrically Erasable PROM (EEPROM): A ROM that can be programmed and erased electrically in-circuit.

FLASH Memory

FLASH Memory is an ideal memory that has high density, read/write capability, is non-volatile, has fast access time, and is cost-effective. It exhibits the key characteristics of both RAM and ROM. Its high-density cell is implemented using a single floating-gate MOS transistor. A data bit is stored as the presence of a charge (logic 0) or the absence of a charge (logic 1) on the floating gate. The amount of charge determines whether the transistor will turn on when a control voltage is applied.

🔑 Definition — FLASH Memory: A non-volatile memory with read/write capability, high density, and fast access times.

FLASH Memory Operations

FLASH Memory operations are classified into Programming, Read, and Erase. Programming adds charge to the floating gate of cells that are to store a logic 0, while cells storing a logic 1 remain unchanged. A positive voltage at the Control Gate attracts electrons to the floating gate. During a Read Operation, a positive voltage is applied to the transistor’s control gate. If a negative charge (logic 0) is stored on the gate, the transistor does not turn on (no current = 0). If no charge (logic 1) is stored, the transistor turns on (current = 1). The Erase Operation removes charge from the memory cell by applying a large positive voltage at the source with respect to the control gate, attracting the electrons away from the floating gate. A FLASH memory is erased prior to programming.

🔑 Definition — FLASH Programming: Adding charge to the floating gate of a cell to store a logic 0, while leaving a cell with no charge for a logic 1. 🔑 Definition — FLASH Read: Applying a voltage to the control gate; a cell with stored charge (0) will not conduct current, while a cell without charge (1) will conduct current. 🔑 Definition — FLASH Erase: Removing charge from the floating gate of all cells in a memory block by applying a reverse voltage.

⭐ Key Takeaways

For the final exam, you must be able to distinguish between DRAM refresh methods (Burst vs. Distributed) and types (RAS-only vs. CAS-before-RAS). Understand how FAST Page Mode and EDO DRAM improve read speed compared to standard FPM. For ROM, memorize the programming and erasing capabilities of each type: Mask (permanent), PROM (one-time), EPROM (UV-erasable), and EEPROM (electrically erasable). Crucially, master the FLASH memory operations: programming (charging the floating gate for logic 0), reading (detecting current flow), and erasing (removing charge). Finally, recall that FLASH memory is non-volatile and combines the density and read/write capability of other memory types.

🧠 Quick Revision Questions

1. During a FAST Page Mode read cycle, what happens to the D_OUT data line when CAS goes high, and what must the external system do to avoid losing data?
2. What is the key difference between a RAS-only refresh and a CAS-before-RAS refresh regarding the source of the row address?
3. How does an EDO DRAM overcome the speed limitation of a Fast Page Mode DRAM during consecutive read operations?
4. In the context of a ROM look-up table, what does the 4-bit address represent, and what does the stored 4-bit data value represent in a binary-to-gray code converter?
5. During a FLASH read operation, why does a memory cell storing a logic 0 not produce a current, while a cell storing a logic 1 does?

📘 Lecture 42 — FLASH MEMORY ARRAY

📖 Overview: This lecture covers the internal structure and operation of FLASH memory arrays, explaining how data is stored and read using MOS transistors organized in rows and columns. It also provides a comprehensive summary of various memory types and introduces special memory architectures like FIFO and LIFO, which are crucial for connecting devices operating at different data rates.

🗂️ Topics Covered

The lecture begins with the organization of FLASH Memory Array, detailing the row and column structure, the role of control gates and source terminals, and the read operation based on stored charge. It then provides a Memory Summary table comparing SRAM, DRAM, ROM, EPROM, EEPROM, and FLASH. Following that, it discusses Special Type of Memories, focusing on the First In-First Out (FIFO) memory used as a buffer for devices with different data rates. Finally, it covers the implementation of FIFO memory using shift registers and its alternative implementation using RAM as a circular buffer.

📝 Lecture Summary

FLASH MEMORY ARRAY

The FLASH memory array is organized into rows and columns. The row line connects to the Control Gate of each MOS transistor, which acts as a single-bit storage cell. The number of transistors in a row depends on the data word size; for an 8-bit byte, eight cells are activated by a single row. Only one row is selected at a time. The Source terminals of all transistors in a column are connected to a common column line. Figure 42.1 illustrates this structure.

When a row is selected (e.g., row 2), all transistors with Gates connected to that row line are activated. Current flows through a selected transistor if its corresponding column select line is activated and the transistor Gate has no stored charge. A stored charge on the gate prevents current flow. For example, if column select 0 is activated but the transistor in that column has a stored charge, no current flows. If column select 1 is activated and its transistor has no charge, current flows.

🔑 Definition — Active Load: A component at the end of each column line that produces a voltage drop when current flows.

The presence or absence of current in each column line is detected. Current flow creates a voltage drop across the active load; no current means no voltage drop. A comparator compares the voltage across each active load with a reference voltage. If there is a voltage drop (current flows), the comparator output is 0. If the voltage drop is 0V (no current), the comparator output is 1. Therefore, the comparator output is the inverse of the stored logic value (stored charge = 1, no charge = 0).

💡 Why this matters: The FLASH memory cell uses a single transistor with a floating gate to store charge. The read operation is non-destructive and relies on sensing current, making it fast and suitable for non-volatile storage.

Memory Summary

A summary of memory types and their key characteristics is presented in Table 42.1.

• SRAM: Non-volatile? No. High density? No (requires 6 transistors per latch). Uses one-transistor cell? No. In-system writable? Yes.
• DRAM: Non-volatile? No. High density? Yes (one transistor + one capacitor). Uses one-transistor cell? Yes. In-system writable? Yes.
• ROM: Non-volatile? Yes. High density? Yes. Uses one-transistor cell? Yes. In-system writable? No.
• EPROM: Non-volatile? Yes. High density? Yes. Uses one-transistor cell? Yes. In-system writable? No.
• EEPROM: Non-volatile? Yes. High density? No (requires extra logic). Uses one-transistor cell? No. In-system writable? Yes.
• FLASH: Non-volatile? Yes. High density? Yes. Uses one-transistor cell? Yes. In-system writable? Yes.

Special Type of Memories

Two special memory types are implemented using shift registers: First In-First Out (FIFO) and Last In-First Out (LIFO). These are used in specific applications where data access order is critical.

First In-First Out (FIFO) Memory

FIFO memories are used to connect digital devices operating at different data rates. For example, a fast microprocessor connected directly to a slow keyboard would waste time waiting. A keyboard buffer (a FIFO memory) is used instead. The keyboard writes keystrokes to the buffer, and the microprocessor reads them when it can, without being idle.

🔑 Definition — FIFO Memory: A memory where the first data written is the first data to be read out.

Data is written and read in the same sequence. As shown in Figure 42.2c, data values (7, 9, 1, 0, 3) are written in order. When device B consumes the first two values (7 and 9), the remaining values (1, 0, 3) shift towards the head of the buffer. New data (5, 6, 1, 2) can then be appended.

📌 Example — FIFO Operation: Data produced in sequence 7, 9, 1, 0, 3. The first two values (7 and 9) are consumed. The buffer now contains 1, 0, 3 at the head. Four new values (5, 6, 1, 2) are appended to the empty locations.

FIFO Implementation using Shift Registers

A FIFO can be implemented using shift registers, as shown in Figure 42.3. An Input Buffer holds incoming data. The Shift Register Control circuit shifts the data to its appropriate location. The Input Control Logic activates an Input Ready signal when the buffer can accept new data. Data is output via an Output Buffer. After data is read, the Shift Control shifts the buffer contents towards the right, moving the next data value to the Output Buffer. An Output Ready signal indicates data is available for reading.

Implementing FIFO memory using RAM

For larger buffers, computers implement FIFO memory by reserving a part of their RAM. This is done as a circular buffer (Figure 42.4). Two registers, a Buffer Input Address Register and a Buffer Output Address Register, point to the locations for the next write and next read respectively. These addresses are updated (incremented and wrapped around) as data is written and read.

⭐ Key Takeaways

A FLASH memory cell stores a bit by trapping charge on the gate of a single MOS transistor, and reading is done by sensing current flow through the transistor when its row and column are selected; the comparator output is inverted relative to the stored charge. The comparison table highlights that FLASH memory is unique in combining non-volatility, high density (one transistor per cell), and in-system write ability. FIFO memories are essential for rate-matching between devices and operate on a first-in, first-out principle, implemented either with dedicated shift registers for small buffers or with RAM using a circular buffer for larger systems. The key difference between the shift-register and RAM-based FIFO is that the shift-register physically moves data, while the RAM-based approach updates pointers to logical locations.

🧠 Quick Revision Questions

1. In a FLASH memory array, what is the relationship between the presence of a stored charge on a transistor's gate and the current flow when that cell is selected?
2. What is the output of the comparator (0 or 1) when current flows through a selected cell in a FLASH array?
3. Name four memory types that are both non-volatile and use a one-transistor cell.
4. What is the primary purpose of a FIFO memory in a digital system?
5. In a RAM-based FIFO buffer, what are the two registers used to manage the read and write operations?

📘 Lecture 43 — LAST IN-FIRST OUT (LIFO) MEMORY

📖 Overview: This lecture introduces the concept of Last In-First Out (LIFO) memory, commonly used to implement a stack in computer systems. It explains two primary implementations—shift register-based and RAM-based stacks—and then covers essential memory system design topics including memory maps, memory expansion techniques, and address decoding. The lecture concludes with an introduction to Field Programmable Gate Arrays (FPGAs).

🗂️ Topics Covered

The lecture begins with the concept of LIFO memory and its analogy to a stack of plates. It then covers shift register-based stack implementation followed by the practical RAM-based stack using a Stack Pointer Register. The topics of memory expansion are discussed in detail, including how microprocessors access different data unit sizes. The concept of a Memory Map is introduced to show the division of address space. Practical methods for expanding both data unit size and memory locations using multiple RAM chips are explained. Finally, the lecture covers Address Decoders for selecting memory chips at specific base addresses and introduces the architecture of FPGAs.

📝 Lecture Summary

Last In-First Out (LIFO) Memory

Last In-First Out (LIFO) Memory, or a stack, operates like a stack of plates: the last item placed on top is the first one removed. In a register-based LIFO, data is "pushed down" when stored and "pulled up" when removed. A shift register-based stack uses Parallel In/Parallel Out registers connected so data shifts through them. For example, in a 5-byte LIFO, the first 8-bit value is stored in Register 1. To store a second value, the first is shifted to Register 2, and the second is written into Register 1. A maximum of five values can be stored. The last value stored in Register 1 is read out first, and the remaining values are pulled up.

🔑 Definition — Stack: A LIFO data structure where the last element stored is the first element retrieved. 📌 Example: A five-byte LIFO memory with Registers 1-5. Storing values 7, then 4, then 9: 7 goes to Reg. 1, then is pushed to Reg. 2 to make room for 4. 4 is then pushed to Reg. 3, and 9 goes to Reg. 1. Reading removes 9 first.

RAM Stack

A practical stack for program execution uses RAM memory, known as a RAM Stack. A special Stack Pointer Register stores the address of the stack top in RAM. As data is written (pushed) or read (popped), the Stack Pointer increments or decrements to always point to the top.

🔑 Definition — Stack Pointer Register: A dedicated register that holds the memory address of the current top of the stack. 📌 Example: Initially, the Stack Pointer is 0. Value '7' is stored at address 0. The Stack Pointer increments to 1, and value '4' is stored. After storing 4, 9, and 8, the Stack Pointer points to location 3 (value 8). Reading the top value (8) decrements the pointer back to 2, making 9 the new top.

Memory Expansion

Digital systems require different amounts of RAM and ROM. The total memory supported depends on the size of the microprocessor's address bus. A 16-bit address bus can access 2^16 (65536) unique memory locations. The data bus size determines how many bytes are accessed per address. An 8-bit data bus accesses one byte, while a 16-bit bus accesses two bytes. Modern microprocessors have up to 64-bit data buses. Memory devices are manufactured in fixed sizes (e.g., 1, 4, or 8-bit data units, and specific address ranges). To meet system requirements, these fixed-size chips are connected together.

📐 Formula: Addressable Locations = 2^(number of address bus lines) 📌 Example: A 16-bit address bus can access 2^16 = 65536 locations. A 32-bit address bus can access 2^32 locations.

Memory Map

A Memory Map specifies the total addressable space of a microprocessor and how that space is distributed among RAM, ROM, stack, and buffers. It shows the base address of each memory block.

🔑 Definition — Base Address: The starting address of a memory chip or block within the system's memory map. 📌 Example: A 1 MByte memory map is divided into 16 blocks of 64 Kbytes each. Block 0 (base address 00000H) is for ROM. Block 1 (base address 10000H) is for data RAM. Block 2 (base address 20000H) is for program code RAM. The last block (base address F0000H) is for the stack.

Expanding Data Unit Size

To create a memory with a wider data unit (e.g., 16-bit word), multiple memory chips with narrower data units (e.g., 8-bit byte) are connected in parallel. The address lines of the chips are connected together so the same location is accessed. The data lines of each chip form different parts of the wider data bus. For example, two 4K x 8 RAM chips can form a single 4K x 16 memory. One chip holds the most significant byte (D8-D15) and the other the least significant byte (D0-D7).

📌 Example: Two 4K Byte RAM chips (A0-A11) with 8 data lines each. Their address lines are tied together. Chip A provides the upper byte (D8-D15), and Chip B provides the lower byte (D0-D7). The CS (Chip Select) and R/W lines are also tied together to select both chips simultaneously for a 16-bit read/write.

💡 Why this matters: This technique allows any microprocessor to access data of its native word size, even if individual memory chips are byte-wide.

Expanding Memory Locations

To increase the total number of memory locations, multiple chips are connected in series or by using address lines to select between them. The data lines of the chips are shared, and a higher-order address line is used as a Chip Select to choose which chip is active at a given time.

📌 Example: To create an 8 KByte memory from two 4K Byte chips. The lower 12 address lines (A0-A11) connect to both chips. The 13th address line (A12) is used to select the chip. When A12=0, the first 4K chip (addresses 0-4095) is selected. When A12=1, it selects the second chip (addresses 4096-8191) via a NOT gate.

Expanding Data Unit Size and Memory Locations

Both techniques can be combined. Four 4K x 8 chips can form an 8K x 16 memory. Chips A and B form one 4K x 16 block, and chips C and D form a second 4K x 16 block. The ( \overline{CS} ) lines of A and B are tied together, and the ( \overline{CS} ) lines of C and D are tied together. The A12 address line selects which 4K x 16 block is active.

📌 Example: Chips A & C store the upper byte, B & D store the lower byte. A12=0 selects chips A and B (4K word block 0). A12=1 selects chips C and D (4K word block 1).

Address Decoders

An Address Decoder is a circuit that detects a specific Base Address from the microprocessor's address bus and generates a Chip Select (CS) signal for the appropriate memory chip. This ensures only the desired memory chip responds to a given memory operation. Decoders can be implemented using logic gates (OR, NAND, NOT) or using m x n decoders like 2x4 or 3x8 decoders.

🔑 Definition — Address Decoder: A digital circuit that uses the higher-order address lines to select a specific memory chip based on its assigned memory range. 📌 Example: For three 4KByte chips at base addresses 0000H, 1000H, and 2000H, a 2x4 decoder takes A12 and A13 as inputs. Input 00 selects RAM1 (0000H), 01 selects RAM2 (1000H), and 10 selects RAM3 (2000H). Input 11 is vacant.

Introduction to FPGAs

A Field Programmable Gate Array (FPGA) is a more flexible device than a PLD. Instead of a single AND-OR array, an FPGA contains many Logic Blocks that can be individually programmed. These blocks are connected by programmable Row and Column Interconnects. The logic blocks connect to the outside world through programmable I/O Blocks. This architecture allows for the implementation of very complex digital circuits.

🔑 Definition — FPGA (Field Programmable Gate Array): An integrated circuit containing an array of programmable logic blocks and interconnects that can be configured to perform any digital function.

⭐ Key Takeaways

The LIFO stack is a fundamental data structure implemented either with shift registers or more practically using RAM and a Stack Pointer Register. Memory system design is determined by the microprocessor's address bus (for total addressable locations) and data bus (for data unit size). A Memory Map organizes the address space into regions for ROM, RAM, stack, and other uses. Memory chips can be combined in parallel to expand the data unit size (e.g., two 8-bit chips for a 16-bit word) or in series using an Address Decoder to expand the number of memory locations. Address Decoders, implemented with gates or decoder chips, are essential for selecting specific memory chips at their assigned Base Addresses. Finally, FPGAs offer a more advanced and flexible architecture than PLDs for creating complex digital systems.

🧠 Quick Revision Questions

1. Explain the difference between a shift register-based LIFO memory and a RAM-based stack, including the role of the Stack Pointer Register.
2. A microprocessor has a 20-bit address bus and a 16-bit data bus. What is its total addressable memory space in bytes?
3. How would you use two 4K x 8 RAM chips to create a single 4K x 16 memory? Describe the connections for address, data, and control lines.
4. What is an Address Decoder and why is it necessary when connecting multiple memory chips to a microprocessor?
5. What are the three main components of an FPGA (Logic Blocks, Interconnects, I/O Blocks) and how do they differ from the structure of a simpler PLD?

📘 Lecture 44 — THE LOGIC BLOCK

📖 Overview: This lecture details the internal structure of a Logic Block within programmable logic devices, focusing on the Look-Up Table (LUT) as a fundamental logic function generator. It then transitions to the critical topic of Analogue-to-Digital Conversion (ADC), explaining the necessity, process (sampling, quantization), and two major converter types: the high-speed Flash ADC and the slower but more precise Dual-Slope ADC used in measuring instruments.

🗂️ Topics Covered

The lecture begins by dissecting a Logic Element, explaining its components: the Look-Up Table (LUT), programmable selects, cascade logic, and flip-flop control. It details how an LUT memory implements logic functions and adders. The discussion then shifts to the need for Analogue-to-Digital conversion, covering the sampling and hold process, the Nyquist Criteria, and quantization. Finally, it presents the operational principles of the Flash A/D Converter and the Dual-Slope A/D Converter, including circuit diagrams, operating principles, and an example calculation for the Flash converter.

📝 Lecture Summary

The Logic Element

The Logic Element within a Logic Block features a Look-Up Table (LUT) with 4-inputs that can be programmed as a logic function generator for SOP functions, adders, and comparators. It has Carry In and Carry Out lines for expansion and Cascade Logic for connecting multiple LUTs. Two Programmable selects allow choosing between combinational (LUT) or registered (Flip-Flop) outputs. The Clock/Clear/Preset Select Logic controls the flip-flop's synchronous (Clock) and asynchronous (Clear, Preset) operations.

The Look-Up Table

The Look-Up Table is implemented using a memory element. For a three-variable SOP function, it requires a memory with 8 locations storing a single bit each. The three address lines represent variables A, B, C. Product terms included in the function store a logic 1; missing terms store a logic 0.

🔑 Definition — LUT: A Look-Up Table is a memory element that stores the truth table of a logic function; the input variables act as address lines to select the stored output.

📐 Formula for SOP Implementation: F = Σ(mᵢ) For each minterm mᵢ, the corresponding memory location is programmed to '1'.

📌 Example: For function F = A'BC' + AB'C + ABC (minterms 2, 5, 7), memory locations 2, 5, and 7 store '1', and all others store '0'. When the address (A=0,B=1,C=0) is input, the output F=1.

A single-bit Full-Adder is implemented using a memory with 8 locations, each storing 2 bits (Sum and Carry_out). Address lines are A, B, and Cᵢₙ.

📌 Example: For address 110 (A=1, B=1, Cᵢₙ=0), the stored data output is 01, meaning Sum=0 and Cₒᵤₜ=1.

💡 Why this matters: The LUT allows any arbitrary combinational logic function to be implemented simply by programming memory contents, making FPGAs reconfigurable.

Analogue to Digital Conversion

Real-world quantities (temperature, speech) are analogue (continuous), while digital systems process digital (discrete binary) information. Analogue to Digital (A/D) converters transform analogue signals into digital values for processing. Examples include mobile phones, digital thermometers, digital voltmeters, and CDs. The process involves sampling the analogue signal and holding it stable for conversion.

Sample and Hold Operation

A Sample and Hold circuit samples the analogue signal at regular intervals and holds the value stable for the A/D converter. The Nyquist Criteria states the sampling frequency must be at least twice the maximum frequency of the analogue signal to allow accurate reconstruction. Under-sampling loses information, while over-sampling provides higher accuracy but requires more processing time.

🔑 Definition — Nyquist Criteria: To accurately reconstruct an analogue signal from its samples, the sampling frequency must be at least twice the highest frequency component of the original signal.

📌 Example: An analogue signal with a maximum frequency of 50 Hz must be sampled at a minimum frequency of 100 Hz (Nyquist rate). The sampled voltage must be held stable for the A/D converter to accurately digitize it.

Quantization

Quantization is the process of converting a sampled analogue signal into a digital code. The number of bits used determines the accuracy (resolution). More bits mean more quantization levels and a more precise digital representation.

🔑 Definition — Quantization: Mapping a continuous range of analogue values into a finite set of discrete digital codes.

📌 Example: A 2-bit quantizer has 4 levels (00, 01, 10, 11) for a 0 to 220V signal: 00=0V, 01=0-73V (range), 10=74-146V, 11=147-220V. A 3-bit quantizer has 8 levels, providing finer granularity and higher accuracy. For an analogue signal ranging 0-31V, using a 4-level (2-bit) quantizer results in a coarse staircase representation of the original signal. A 16-level (4-bit) quantizer produces a much closer representation.

Operational Amplifier (Op-Amp)

An Operational Amplifier is a linear amplifier with high voltage gain, high input impedance, and low output impedance. It amplifies the difference between its inverting (-) and non-inverting (+) inputs. It is used as an Inverting Amplifier (gain = -Rf/Ri) and as a Comparator (output saturates to high or low based on which input is larger). A/D converters use Op-Amps as Integrators (by replacing Rf with a capacitor) and Comparators.

Flash Analogue-to Digital Converter

The Flash A/D Converter uses a resistor potential divider to create reference voltages for multiple Op-Amp comparators. The analogue input is applied to all comparators simultaneously. The comparator outputs drive a priority encoder that produces the binary output.

🔑 Definition — Flash A/D Converter: The fastest type of ADC, using a parallel bank of comparators to simultaneously compare the input voltage against a set of reference voltages.

📌 Example (3-bit Flash Converter with Vᵣₑբ = 8V): For an input of 4.2V, reference voltages are 7V, 6V, 5V, 4V, 3V, 2V, 1V. The comparators with reference voltages 1V, 2V, 3V output '1' (input > ref). Comparators with 4V, 5V, 6V, 7V output '0'. This binary pattern is encoded by the priority encoder to the binary value 100 (decimal 4).

A large number of comparators are required (2ⁿ - 1 for n-bit). For a 4-bit converter, 15 comparators are needed. Flash converters are used for high-speed applications like video signal conversion but are expensive and power-hungry.

Dual-Slope Analogue to Digital Converter

The Dual-Slope A/D Converter is slower but accurate, commonly used in digital voltmeters. It integrates the input voltage for a fixed time, then discharges the integrator with a known negative reference voltage. The time to discharge is proportional to the input voltage and is measured by a counter.

🔑 Definition — Dual-Slope A/D Converter: An ADC that converts an analogue voltage to a digital value by measuring the time required for an integrator to discharge from a voltage level proportional to the input.

📌 Operation:

1. Phase 1 (Integration): Switch connects to Vᵢₙ. Capacitor charges, creating a negative ramp at integrator output. Counter counts up from 0 for a fixed period n (until terminal count).
2. Phase 2 (De-integration): At t=n, switch connects to -Vᵣₑբ. Capacitor discharges, creating a positive ramp at integrator output. Counter continues counting from 0.
3. Termination: When integrator output reaches 0V, comparator disables the clock, and counter stops at count m.
4. Result: The count m is proportional to the input voltage Vᵢₙ.

Higher Vᵢₙ → more charge on capacitor → longer discharge time m → larger count value.

⭐ Key Takeaways

You must remember that the Look-Up Table is the core of a logic block, implementing any combinational function by storing its truth table in memory. For Analogue-to-Digital conversion, the Nyquist Criteria dictates the minimum sampling frequency must be twice the signal's highest frequency. Quantization resolution, determined by the number of bits, directly impacts accuracy. The Flash ADC provides the fastest conversion using parallel comparators but is expensive, while the Dual-Slope ADC offers high accuracy by measuring the time to discharge an integrator, making it ideal for instruments like voltmeters.

🧠 Quick Revision Questions

1. What are the two programmable selects in a Logic Element and what do they select between?
2. Explain how a 4-input Look-Up Table can be used to implement a full adder function.
3. What is the Nyquist Criteria and why is it important in A/D conversion?
4. Describe the operation of a 3-bit Flash A/D converter. How many comparators does it require and why?
5. Explain the two phases of operation in a Dual-Slope A/D converter and how the counter value represents the input voltage.

📘 Lecture 45 — Successive-Approximation Analogue to Digital Converter

📖 Overview: This lecture covers the Successive-Approximation A/D converter, the most commonly used type for converting analogue signals to binary values. It explains its operation, components, and conversion process, then details common A/D converter errors and concludes with an in-depth look at Digital to Analogue Converters and their performance characteristics. Understanding this converter is crucial for applications requiring a balance of speed and accuracy.

🗂️ Topics Covered

The lecture begins with the Successive-Approximation A/D converter, detailing its components (SAR, DAC, Comparator) and step-by-step conversion process with a 5.2V example. It then discusses three types of Analogue-to-Digital Converter Errors: Missing Code, Incorrect Code, and Offset Error. The latter half covers Digital to Analogue Conversion, focusing on the Binary-Weighted-Input D/A Converter and the R/2R Ladder D/A Converter, concluding with five key performance characteristics: Resolution, Accuracy, Linearity, Monotonicity, and Settling Time.

📝 Lecture Summary

Successive-Approximation Analogue to Digital Converter

The Successive-Approximation A/D converter is the most commonly used A/D converter because it has a fixed conversion time and is faster than the Dual-Slope converter, though slower than the Flash converter. Its main components are the Successive Approximation Register (SAR), a Digital to Analogue Converter, and a Comparator. The analogue signal sample is applied to the comparator's non-inverting input. Initially, the SAR sets the most significant bit (MSB) to logic 1. The DAC converts this binary value to its equivalent analogue voltage, which is applied to the comparator's inverting input. If the input signal is larger, the comparator outputs logic 1, setting the MSB; otherwise, it resets it. This process repeats for all bits, with the SAR setting or resetting each bit based on the comparator's output.

🔑 Definition — Successive-Approximation A/D Converter: An A/D converter that uses a binary search algorithm by comparing the input voltage with the output of a DAC controlled by a SAR to find the closest binary representation. 📌 Example: Converting 5.2V with a 4-bit A/D converter (quantization steps of 1V). The process is shown in Table 45.1. The SAR first tries 1000 (8V), which is too high, so it resets the MSB. It then tries 0100 (4V), which is too low, so it keeps that bit. Next, it tries 0110 (6V), which is too high, so it resets that bit. Finally, it tries 0101 (5V), which is less than 5.2V, so the final binary output is 0101.

💡 Why this matters: The conversion time is fixed and depends on the number of bits (e.g., a 6-bit converter completes in 6 clock periods), making it predictable.

Analogue-to-Digital Converter Errors

A/D converters exhibit three types of errors: Missing Code, Incorrect Code, and Offset Error. These are typically tested using an ideal linear ramp input signal.

1. Missing Code: This error occurs when a specific binary code is skipped in the output sequence. For example, in Figure 45.2a, the code '1001' is missing, and the output jumps from '1000' to '1010'. In a Flash converter, this is due to a failed comparator, causing the Priority Encoder to output the same code for two different analogue values.
2. Incorrect Code: This error results from a particular bit being "stuck" at a fixed logic value (0 or 1). In Figure 45.2b, the bit next to the LSB is stuck at logic 0. This means analogue values 2 and 3 both produce the output '0000' and '0001' instead of '0010' and '0011', respectively.
3. Offset Error: This error occurs when the binary output consistently represents a value higher than the actual analogue input. It is caused by a fault in the comparator circuit. The offset error can be compensated for, but missing and incorrect codes cannot.

📌 Example: Figure 45.2c illustrates an offset error of 2 volts. For every analogue input, the corresponding binary output represents a value that is exactly 2V higher.

Digital to Analogue Conversion

Digital binary signals are converted into analogue signals using D/A Converters. The two main types are the Binary-Weighted-Input D/A Converter and the R/2R Ladder D/A Converter.

Binary-Weighted-Input Digital to Analogue Converter

This converter uses a summing amplifier (Op-Amp) with a resistor network where each resistor's value represents the binary weight of its corresponding input bit. The current through each resistor is summed at the inverting input, and the output voltage is determined by the voltage drop across the feedback resistor (Rf).

🔑 Definition — Binary-Weighted-Input D/A Converter: A D/A converter that uses a set of resistors with values proportional to the binary weights (e.g., R, 2R, 4R, 8R) of the input bits to generate a weighted sum of currents. 📌 Example: For a 4-bit converter with resistors 1K (bit 0), 2K (bit 1), 4K (bit 2), and 8K (bit 3), and a feedback resistor of 2K ohms. If the input is 1000 (8 decimal), only the MSB (bit 3) is high (5V). Current = 5V / 8K = 0.625 mA. The total current through Rf is 0.625 mA. Vout = -(0.625 mA * 2K) = -1.25V. A full table of outputs is given in Table 45.2.

📐 Formula: Vout = -Rf * (V/R * bit0 + V/2R * bit1 + V/4R * bit2 + V/8R * bit3) 🔑 Important Note: This converter is not practical for many bits because it requires resistors with exact values that are multiples of each other, which is difficult to manufacture accurately.

The R/2R Ladder Digital to Analogue Converter

This converter overcomes the problem of needing many weighted resistors by using a ladder network with only two resistor values: R and 2R. The circuit's output voltage is determined by the Thevenin equivalent circuit of the ladder network for a given binary input.

🔑 Definition — R/2R Ladder D/A Converter: A D/A converter that uses a network of resistors with only two values (R and 2R) to generate precise analogue voltages from binary inputs. It is easier to manufacture accurately. 📌 Example: For binary input 0001, the simplified Thevenin equivalent circuit (Figures 45.5a and 45.5b) has a Thevenin voltage (Vth) of 0.625V and a series resistance of R. The current through Rf is I = 0.625V / 2R, and Vout = -I * Rf. Table 45.3 shows the outputs for all 16 combinations.

Performance characteristics of Digital-to-Analogue Converters

The performance of D/A converters is determined by five key parameters:

1. Resolution: The number of bits the converter can process. It is also expressed as the reciprocal of the number of discrete output steps as a percentage. For a 4-bit converter, resolution = (1/15) * 100 = 6.67%.

2. Accuracy: How close the actual output is to the expected output, expressed as a percentage of the full-scale output. Ideally, the accuracy should be ±1/2 of the least significant bit (LSB). For an 8-bit converter with a full-scale of 64V, the LSB is 0.25V (250mV). The maximum allowed error is ±125mV.

3. Linearity: The output voltage should form a straight line when plotted against the binary input. An offset error is indicated by a non-zero output when all input bits are 0.

4. Monotonicity: The output should always increase as the binary input increases. If the output ever decreases for an increased input, the converter exhibits non-monotonic behavior.

5. Settling Time: The time the D/A converter takes to settle within ±1/2 LSB of its final value after a change in the binary input. For example, if the output changes from 1.250V to 250mV but reaches 375mV (±1/2 LSB) in 20 msec, the settling time is 20 msec.

⭐ Key Takeaways

The Successive-Approximation A/D converter is a widely used converter that uses a binary search algorithm with an SAR, DAC, and comparator. Its conversion time is fixed and depends on the number of bits. A/D converter errors include Missing Code (failed comparator), Incorrect Code (stuck bit), and Offset Error (comparator fault), which can sometimes be compensated. For D/A conversion, the Binary-Weighted-Input method is simple but impractical for many bits, while the R/2R Ladder method is preferred for its use of only two resistor values. Key D/A converter performance specs include Resolution, Accuracy (ideally ≤ ±1/2 LSB), Linearity, Monotonicity, and Settling Time.

🧠 Quick Revision Questions

1. What are the three main components of a Successive-Approximation A/D converter?
2. In the conversion example (5.2V to 4-bit binary), why did the SAR reset the MSB during the first step?
3. What is the primary cause of a "Missing Code" error in a Flash A/D converter?
4. What is the main advantage of the R/2R Ladder D/A converter over the Binary-Weighted-Input D/A converter?
5. For an 8-bit D/A converter with a full-scale output of 10V, what is the maximum allowed error in mV for an output to be considered accurate ((\pm 1/2) LSB)?