VU Final Term Past Papers
104 solved final term past paper MCQs for CS501 (Advanced Computer Architecture) at Virtual University, each with the correct answer marked. Use them to learn the VU question style and test your recall. An independent study tool — not affiliated with VU.
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Q1. Type A format of SRC uses instructions
Q2. The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
Q3. Which one of the following are the code size and the Number of memory bytes respectively for a 2-address instruction?
Q4. Which operator is used to name registers, or part of registers, in the Register Transfer Language?
Q5. The transmission of data in which each character is self-contained units with its own start and stop bits is ------
Q6. Circuitry that is used to move data is called -------------
Q7. Which one of the following is NOT a technique used when the CPU wants to exchange data with a peripheral device?
Q8. Every time you press a key, an interrupt is generated. This is an example of
Q9. The interrupts which are pre-programmed and the processor automatically finds the address of the ISR using interrupt vector table are
Q10. Which is the last instruction of the ISR that is to be executed when the ISR terminates?
Q11. If NMI and INTR both interrupts occur simultaneously, then which one has the precedence over the other
Q12. Identify the following type of serial communication error condition: The prior character that was received was not still read by the CPU and is over written by a new received character.
Q13. ----------the device usually means reading its status register every so often until the device's status changes to indicate that it has completed the request.
Q14. Which I/O technique will be used by a sound card that may need to access data stored in the computer's RAM?
Q15. For increased and better performance we use which are usually made of glass.
Q16. In if we find some call party busy we can have provision of call waiting.
Q17. In technique memory is divided into segments of variable sizes depending upon the requirements.
Q18. For a request of data if the requested data is not present in the cache, it is called a
Q19. An entire memory can be erased in one or a few seconds which is much faster than EPROM.
Q20. The signal coming from the CPU tells the memory that some interaction is required between the CPU and memory.
Q21. In Multiple Interrupt Line, a number of interrupt lines are provided between the modules.
Q22. The data movement instructions data within the machine and to or from input/output devices.
Q23. CRC has ----- overhead as compared to Hamming code.
Q24. The ________ is w-bit wide and contains a data word, directly connected to the data bus which is b-bit wide memory address register (MAR) .
Q25. In technique, a particular block of data from main memory can be placed in only one location into the cache memory .
Q26. The _____________ RTN describes the overall effect of instructions on the programmer visible registers.
Q27. The instruction set is of _____________ importance in governing the structure and function of the pipeline.
Q28. A provides four functions: Select, DataIn, DataOut and Read/Write.
Q29. We can classify or partition the SRC instructions by their overall ______________ behavior.
Q30. The ____________ RTN describes detailed register transfer steps in the data path that produce the overall effect.
Q31. All members of the MC68000 family are ____________ processors.
Q32. _________ Operations refers to a processor that can issue more than one instruction simultaneously.
Q33. Exceptions which are _______________ occur in response to events that are paced by the internal processor clock.
Q34. 1-bit sign, 8-bit exponent, 23-bit fraction and a bias of 127 is used for Binary Floating Point Representation
Q35. Where does the processor store the address of the first instruction of the ISR?
Q36. In , a separate address space of the CPU is reserved for I/O operations.
Q37. -------------- is the time needed by the CPU to recognize (not service) an interrupt request.
Q38. Identify the type of serial communication error condition in which A 0 is received instead of a stop bit (which is always a 1)?
Q39. The conversion of numbers from a representation in one base to another is known as_______
Q40. How Interrupt driven I/O is better than polling because?
Q41. In Single-Precision Binary Floating Point Representation the exponent is
Q42. The______is m-bits wide and contains memory address generated by the CPU directly connected to the m-bit wide address bus Booth Recording
Q43. A combination of parallel and sequential hardware used to build a multiplier is known as _______
Q44. The register file is a collection of bit wide registers used for data transfer between memory and the CPU .
Q45. The of an m digit number x is xc’=bm -1- x
Q46. In ____ recording ,bits are encoded in pairs so there are only ' n/2' additions instead of 'n'.
Q47. Biased Representation 133. For of an error we just need to know that there exists an error.
Q48. In Double-Precision Binary Floating Representation the function is
Q49. In computers, floating-point representation uses to encode significand, exponent and their sign in a single word
Q50. Which one of the following portions of an instruction represents the operation to be performed?
Q51. What is the instruction length of the FALCON-E processor?
Q52. Which type of instructions enables mathematical computations?
Q53. What is the instruction length of the SRC and Falcon E processor?
Q54. An instruction that specifies one operand in memory and one operand in a register would be known as a ______ address instruction.
Q55. In floating point representations is also called mantissa.
Q56. What should be the behavior of interrupts during critical sections?
Q57. Which one of the following is a binary cell capable of storing one bit of information?
Q58. Which type of instructions load data from memory into registers, or store data from registers into memory and transfer data between different kinds of special-purpose registers?
Q59. What does the RTL expression [M(1234)] means?
Q60. Which one of the following languages presents a simple, human-oriented language to specify the operations, register communication and timing of the steps that take place within a CPU to carry out higher level (user programmable) instructions?
Q61. Which one of the following instructions is used to load register from memory using a relative address?
Q62. Taking control of the system bus for a few bus cycles is known as .
Q63. In-------------address mode, the actual data is stored in the instruction.
Q64. Keyboard Interrupt (INT 9) is an example of ----- interrupt.
Q65. By which file extension does the FALCON-A Assembler loads a FALCON-A assembly file?
Q66. All ----------interrupts have priority over all interrupts
Q67. The can also be used anywhere in the source file to force code at a particular address in the memory.
Q68. In which one of the following addressing modes, the operand does not specify an address but it is the actual data to be used.
Q69. When is the “Divide error interrupt‖ generated?
Q70. Which one of the following is a term used to describe a storage systems' resilience to disk failure through the use of multiple disks and by the use of data distribution and correction techniques?
Q71. Falcon-A Simulator loads a FALCON-A binary file with a extension and presents its contents into different areas of the simulator.
Q72. For of an error we just need to know that there exists an error.
Q73. Identify the type of serial communication error condition in which 0 is received instead of a stop bit (which is always a 1)?
Q74. Raid Level is not a true member of the RAID family.
Q75. Which one of the following is an address (binary bit pattern) issued by CPU?
Q76. Which one the following interrupts is initiated with an INT instruction?
Q77. An -----------is a program that takes basic computer instructions and converts them into a pattern of bits that the computer's processor can use to perform its basic operations.
Q78. Which format of the instruction is called the accumulator?
Q79. ________chips have quartz windows and by applying ultraviolet light data can be erased from them.
Q80. ______ is a combination of arithmetic, logic and shifter unit along with some multiplexers and control unit.
Q81. 16k x4 static RAM Chip is arranged in the form of four _____________ cells.
Q82. In a DRAM cell, the storage capacitor will discharge in around ______________
Q83. _________ is a technique in which some of the CPU’s address lines forming an input to the address decoder are ignored.
Q84. An interface that can be used to connect the microcomputer bus to ________is called an I/O Port.
Q85. Which one of the following methods for resolving the priority makes use of individual bits of a priority encoder?
Q86. Identify the following type of serial communication error condition in which no character is available at the beginning of an interval.
Q87. In which one of the following interrupts the device have to supply the address of the subroutine to the
Q88. Shifting of the radix point towards left or right is called ________
Q89. _______ are computed by the ALU and stored in processor status register.
Q90. A _______signal decides whether the input word should be shifted or bypassed
Q91. ____ signal is high, this would correspond to a read operation equivalent to having an input data to the CPU and output from the memory REQUEST .
Q92. Given an m-digit base b number x, the ______ of x is xc = ( bm– x) mod bm
Q93. _____ is the simplest form for representing a signed number
Q94. _______ control signal enable the input to the PC for receiving a value that is currently on the internal processor bus.
Q95. All ----------interrupts have priority over all ---------interrupt
Q96. In this figure, the constant value specified by the immediate field is added to the register value, and the resultant is the index of memory location that is referred i.e. Effective Address = A + (content of R) . Identify the addressing mode.
Q97. ___________ is the time for first bit of the message to arrive at the receiver including delays.
Q98. Which one of the following is the memory organization of SRC processor?
Q99. _______ indicate the availability of page in main memory.
Q100. ____________ is the most general and least useful performance metrics for RISC machines.
Q101. Advance Computer Architecture Solved MCQS Feb 05,2013 From Midterm Papers CS501- Advance Computer Architecture
Q102. ADVANCE COMPUTER ARCHITECTURE
Q103. Advance Computer Architecture Solved MCQS Feb 22,2013 CS501- Advance Computer Architecture
Q104. __________ is/are defined as the number of instructions processed per second